Rev. 1.50, 10/04, page 127 of 448
Bit Bit Name
Initial
Value R/W Description
15 to 10 URC All 0 R/W UTLB Replace Counter
These bits serve as a random counter for indicating the
UTLB entry for which replacement is to be performed
with an LDTLB instruction. This bit is incremented each
time the UTLB is accessed. If URB > 0, URC is cleared
to 0 when the condition URC = URB is satisfied. Also
note that if a value is written to URC by software which
results in the condition of URC ≥ URB, incrementing is
first performed in excess of URB until URC = H'3F.
URC is not incremented by an LDTLB instruction.
9 SQMD 0 R/W Store Queue Mode Bit
Specifies the right of access to the store queues.
0: User/privileged access possible
1: Privileged access possible (address error exception
in case of user access)
8 SV 0 R/W Single Virtual Memory Mode/Multiple Virtual Memory
Mode Switching Bit
When this bit is changed, ensure that 1 is also written to
the TI bit.
0: Multiple virtual memory mode
1: Single virtual memory mode
7 to 3  All 0 R Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
2 TI 0 R/W TLB Invalidate Bit
Writing 1 to this bit invalidates (clears to 0) all valid
UTLB/ITLB bits. This bit is always read as 0.
1  0 R Reserved
For details on reading from or writing to this bit, see
description in General Precautions on Handling of
Product.
0 AT 0 R/W Address Translation Enable Bit
These bits enable or disable the MMU.
0: MMU disabled
1: MMU enabled
MMU exceptions are not generated when the AT bit is
0. In the case of software that does not use the MMU,
the AT bit should be cleared to 0.
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