Renesas SuperH SH-4A - Page 15

Rev. 1.50, 10/04, page xv of xx
10.2.2 BSRF (Branch to Subroutine Far): Branch Instruction
(Delayed Branch Instruction)............................................................................... 344
10.2.3 JSR (Jump to Subroutine): Branch Instruction (Delayed Branch Instruction)..... 346
10.2.4 LDC (Load to Control Register): System Control Instruction
(Privileged Instruction) ........................................................................................ 348
10.2.5 LDS (Load to FPU System register): System Control Instruction....................... 349
10.2.6 STC (Store Control Register): System Control Instruction
(Privileged Instruction) ........................................................................................ 351
10.2.7 STS (Store from FPU System Register): System Control Instruction .................352
10.3 FPU Instruction.................................................................................................................354
10.3.1 FABS (Floating-point Absolute Value): Floating-Point Instruction.................... 365
10.3.2 FADD (Floating-point ADD): Floating-Point Instruction ................................... 366
10.3.3 FCMP (Floating-point Compare): Floating-Point Instruction.............................. 369
10.3.4 FCNVDS (Floating-point Convert Double to Single Precision):
Floating-Point Instruction .................................................................................... 373
10.3.5 FCNVSD (Floating-point Convert Single to Double Precision):
Floating-Point Instruction .................................................................................... 376
10.3.6 FDIV (Floating-point Divide): Floating-Point Instruction................................... 378
10.3.7 FIPR (Floating-point Inner Product): Floating-Point Instruction......................... 382
10.3.8 FLDI0 (Floating-point Load Immediate 0.0): Floating-Point Instruction............ 384
10.3.9 FLDI1 (Floating-point Load Immediate 1.0): Floating-Point Instruction............ 385
10.3.10 FLDS (Floating-point Load to System register): Floating-Point Instruction ...... 386
10.3.11 FLOAT (Floating-point Convert from Integer): Floating-Point Instruction ........ 387
10.3.12 FMAC (Floating-point Multiply and Accumulate): Floating-Point Instruction... 389
10.3.13 FMOV (Floating-point Move): Floating-Point Instruction.................................. 395
10.3.14 FMOV (Floating-point Move Extension): Floating-Point Instruction ................. 399
10.3.15 FMUL (Floating-point Multiply): Floating-Point Instruction..............................402
10.3.16 FNEG (Floating-point Negate Value): Floating-Point Instruction....................... 405
10.3.17 FPCHG (Pr-bit Change): Floating-Point Instruction ........................................... 406
10.3.18 FRCHG (FR-bit Change): Floating-Point Instruction.......................................... 407
10.3.19 FSCA (Floating Point Sine And Cosine Approximate):
Floating-Point Instruction .................................................................................... 408
10.3.20 FSCHG (Sz-bit Change): Floating-Point Instruction ........................................... 410
10.3.21 FSQRT (Floating-point Square Root): Floating-Point Instruction....................... 411
10.3.22 FSRRA (Floating Point Square Reciprocal Approximate):
Floating-Point Instruction ................................................................................... 414
10.3.23 FSTS (Floating-point Store System Register): Floating-Point Instruction .......... 416
10.3.24 FSUB (Floating-point Subtract): Floating-Point Instruction................................417
10.3.25 FTRC (Floating-point Truncate and Convert to integer):
Floating-Point Instruction .................................................................................... 420
10.3.26 FTRV (Floating-point Transform Vector): Floating-Point Instruction ................ 423