Renesas SuperH SH-4A - Page 14

Rev. 1.50, 10/04, page xiv of xx
10.1.44 NEGC (Negate with Carry): Arithmetic Instruction............................................ 287
10.1.45 NOP (No Operation): System Control Instruction............................................... 288
10.1.46 NOT (Not-logical Complement): Logical Instruction ......................................... 289
10.1.47 OCBI (Operand Cache Block Invalidate): Data Transfer Instruction.................. 290
10.1.48 OCBP (Operand Cache Block Purge): Data Transfer Instruction........................ 291
10.1.49 OCBWB (Operand Cache Block Write Back): Data Transfer Instruction........... 292
10.1.50 OR (OR Logical): Logical Instruction................................................................. 293
10.1.51 PREF (Prefetch Data to Cache): Data Transfer Instruction ................................. 296
10.1.52 PREFI (Prefetch Instruction Cache Block): Data Transfer Instruction................ 297
10.1.53 ROTCL (Rotate with Carry Left): Shift Instruction ............................................ 298
10.1.54 ROTCR (Rotate with Carry Right): Shift Instruction.......................................... 299
10.1.55 ROTL (Rotate Left): Shift Instruction ................................................................. 300
10.1.56 ROTR (Rotate Right): Shift Instruction............................................................... 301
10.1.57 RTE (Return from Exception): System Control Instruction ................................ 302
10.1.58 RTS (Return from Subroutine): Branch Instruction............................................. 304
10.1.59 SETS (Set S Bit): System Control Instruction ..................................................... 306
10.1.60 SETT (Set T Bit): System Control Instruction..................................................... 307
10.1.61 SHAD (Shift Arithmetic Dynamically): Shift Instruction ................................... 308
10.1.62 SHAL (Shift Arithmetic Left): Shift Instruction.................................................. 310
10.1.63 SHAR (Shift Arithmetic Right): Shift Instruction ............................................... 311
10.1.64 SHLD (Shift Logical Dynamically): Shift Instruction......................................... 312
10.1.65 SHLL (Shift Logical Left ): Shift Instruction ...................................................... 314
10.1.66 SHLLn (n bits Shift Logical Left): Shift Instruction ........................................... 315
10.1.67 SHLR (Shift Logical Right): Shift Instruction..................................................... 317
10.1.68 SHLRn (n bits Shift Logical Right): Shift Instruction......................................... 318
10.1.69 SLEEP (Sleep): System Control Instruction (Privileged Instruction).................. 320
10.1.70 STC (Store Control Register): System Control Instruction
(Privileged Instruction)........................................................................................ 321
10.1.71 STS (Store System Register): System Control Instruction .................................. 325
10.1.72 SUB (Subtract Binary): Arithmetic Instruction ................................................... 327
10.1.73 SUBC (Subtract with Carry): Arithmetic Instruction .......................................... 328
10.1.74 SUBV (Subtract with (V flag) Underflow Check): Arithmetic Instruction ......... 329
10.1.75 SWAP (Swap Register Halves): Data Transfer Instruction ................................. 331
10.1.76 SYNCO (Synchronize Data Operation): Data Transfer Instruction..................... 333
10.1.77 TAS (Test And Set): Logical Instruction............................................................. 334
10.1.78 TRAPA (Trap Always): System Control Instruction........................................... 336
10.1.79 TST (Test Logical): Logical Instruction .............................................................. 337
10.1.80 XOR (Exclusive OR Logical): Logical Instruction ............................................. 339
10.1.81 XTRCT (Extract): Data Transfer Instruction....................................................... 341
10.2 CPU Instructions (FPU related) ........................................................................................ 342
10.2.1 BSR (Branch to Subroutine): Branch Instruction
(Delayed Branch Instruction)............................................................................... 342