Renesas SuperH SH-4A - Page 18

Rev. 1.50, 10/04, page xviii of xx
Figure 7.9 Flowchart of Memory Access Using UTLB.............................................................. 134
Figure 7.10 Flowchart of Memory Access Using ITLB ............................................................. 135
Figure 7.11 Operation of LDTLB Instruction............................................................................. 138
Figure 7.12 Memory-Mapped ITLB Address Array................................................................... 147
Figure 7.13 Memory-Mapped ITLB Data Array ........................................................................ 148
Figure 7.14 Memory-Mapped UTLB Address Array ................................................................. 150
Figure 7.15 Memory-Mapped UTLB Data Array....................................................................... 151
Figure 7.16 Physical Address Space (32-Bit Address Extended Mode)..................................... 151
Figure 7.17 PMB Configuration.................................................................................................152
Figure 7.18 Memory-Mapped PMB Address Array ................................................................... 155
Figure 7.19 Memory-Mapped PMB Data Array......................................................................... 156
Section 8 Caches
Figure 8.1 Configuration of Operand Cache (OC) ..................................................................... 160
Figure 8.2 Configuration of Instruction Cache (IC) ................................................................... 161
Figure 8.3 Configuration of Write-Back Buffer ......................................................................... 172
Figure 8.4 Configuration of Write-Through Buffer.................................................................... 172
Figure 8.5 Memory-Mapped IC Address Array ......................................................................... 178
Figure 8.6 Memory-Mapped IC Data Array............................................................................... 179
Figure 8.7 Memory-Mapped OC Address Array........................................................................ 180
Figure 8.8 Memory-Mapped OC Data Array ............................................................................. 181
Figure 8.9 Store Queue Configuration........................................................................................ 182
Appendix
Figure B.1 Instruction Prefetch................................................................................................... 433