Renesas SuperH SH-4A - Page 19

Rev. 1.50, 10/04, page xix of xx
Tables
Section 1 Overview
Table 1.1 Features.....................................................................................................................1
Table 1.2 Changes from SH-4 to SH-4A .................................................................................. 4
Section 2 Programming Model
Table 2.1 Initial Register Values...............................................................................................9
Table 2.2 Bit Allocation for FPU Exception Handling........................................................... 19
Section 3 Instruction Set
Table 3.1 Execution Order of Delayed Branch Instructions ................................................... 23
Table 3.2 Addressing Modes and Effective Addresses........................................................... 25
Table 3.3 Notation Used in Instruction List............................................................................ 29
Table 3.4 Fixed-Point Transfer Instructions ........................................................................... 31
Table 3.5 Arithmetic Operation Instructions .......................................................................... 33
Table 3.6 Logic Operation Instructions .................................................................................. 35
Table 3.7 Shift Instructions.....................................................................................................36
Table 3.8 Branch Instructions................................................................................................. 37
Table 3.9 System Control Instructions.................................................................................... 37
Table 3.10 Floating-Point Single-Precision Instructions .......................................................... 40
Table 3.11 Floating-Point Double-Precision Instructions.........................................................41
Table 3.12 Floating-Point Control Instructions ........................................................................41
Table 3.13 Floating-Point Graphics Acceleration Instructions.................................................42
Section 4 Pipelining
Table 4.1 Representations of Instruction Execution Patterns..................................................44
Table 4.2 Instruction Groups .................................................................................................. 54
Table 4.3 Combination of Preceding and Following Instructions........................................... 55
Table 4.4 Issue Rates and Execution Cycles........................................................................... 57
Section 5 Exception Handling
Table 5.1 Register Configuration............................................................................................ 65
Table 5.2 States of Register in Each Operating Mode ............................................................ 65
Table 5.3 Exceptions...............................................................................................................70
Section 6 Floating-Point Unit (FPU)
Table 6.1 Floating-Point Number Formats and Parameters.................................................... 99
Table 6.2 Floating-Point Ranges........................................................................................... 100
Table 6.3 Bit Allocation for FPU Exception Handling......................................................... 107
Section 7 Memory Management Unit (MMU)
Table 7.1 Register Configuration.......................................................................................... 121
Table 7.2 Register States in Each Processing State ..............................................................121