Rev. 1.50, 10/04, page 233 of 448
Example 2:
; R1:R2 (64 bits) ÷ R0 (32 bits) = R2 (32 bits); unsigned
TST R0,R0 ;Check for division by zero
BT ZERO_DIV ;
CMP/HS R0,R1 ;Check for overflow
BT OVER_DIV ;
DIV0U ;Flag initialization
.arepeat 32 ;
ROTCL R2 ;Repeat 32 times
DIV1 R0,R1 ;
.aendr ;
ROTCL R2 ;R2 = quotient
Example 3:
;R1 (16 bits) ÷ R0 (16 bits) = R1 (16 bits); signed
SHLL16 R0 ;Set divisor in upper 16 bits, clear lower 16 bits to 0
EXTS.W R1,R1 ;Dividend sign-extended to 32 bits
XOR R2,R2 ;R2 = 0
MOV R1,R3 ;
ROTCL R3 ;
SUBC R2,R1 ;If dividend is negative, subtract 1
DIV0S R0,R1 ;Flag initialization
.arepeat 16 ;
DIV1 R0,R1 ;Repeat 16 times
.aendr ;
EXTS.W R1,R1 ;
ROTCL R1 ;R1 = quotient (one's complement notation)
ADDC R2,R1 ;If MSB of quotient is 1, add 1 to convert to two's complement notation
EXTS.W R1,R1 ;R1 = quotient (two's complement notation)
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