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Renesas SuperH SH-4A - Page 254

Renesas SuperH SH-4A
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Rev. 1.50, 10/04, page 234 of 448
Example 4:
;R2 (32 bits) ÷ R0 (32 bits) = R2 (32 bits); signed
MOV R2,R3 ;
ROTCL R3 ;
SUBC R1,R1 ;Dividend sign-extended to 64 bits (R1:R2)
XOR R3,R3 ;R3 = 0
SUBC R3,R2 ;If dividend is negative, subtract 1 to convert to one's complement notation
DIV0S R0,R1 ;Flag initialization
.arepeat 32 ;
ROTCL R2 ;Repeat 32 times
DIV1 R0,R1 ;
.aendr ;
ROTCL R2 ;R2 = quotient (one's complement notation)
ADDC R3,R2 ;If MSB of quotient is 1, add 1 to convert to two's complement notation
;R2 = quotient (two's complement notation)

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