Renesas SuperH SH-4A User Manual

Rev. 1.50, 10/04, page 442 of 448
Item Page Revision (See Manual for Details)
10.1.4 AND (AND Logical)
• Possible Exceptions
209 Added.
Exceptions are checked taking a data access by this
instruction as a byte load and a byte store.
10.1.50 OR (OR Logical)
• Possible Exceptions
295 Added.
Exceptions are checked taking a data access by this
instruction as a byte load and a byte store.
Amended.
This instruction does not generate data address error
and MMU exceptions except data TLB multiple-hit
exception. In the event of an error, the PREF
instruction is treated as an NOP (no operation)
instruction.
10.1.51 PREF (Prefetch Data to
Cache)
• Description
• Possible Exceptions:
296
Added.
• Data TLB multiple-hit exception
10.1.52 PREFI (Prefetch
Instruction Cache Block)
297 Amended.
This instruction does not generate data address error
and MMU exceptions. In the event of an error, the
PREFI instruction is treated as an NOP (no operation)
instruction.
10.1.76 SYNCO (Synchronize
Data Operation)
333 Amended.
Format Operation
SYNCO
Data accesses invoked by the following
instruction are not executed until execution of
data accesses which precede this instruction
has been completed.
10.1.76 SYNCO (Synchronize
Data Operation)
• Description
333 Amended.
This instruction is used to synchronize data operations.
When this instruction is executed, the subsequent bus
accesses are not executed until the execution of all
preceding bus accesses has been completed.
10.1.76 SYNCO (Synchronize
Data Operation)
• Notes
333 Changed.
The SYNCO instruction can not guarantee the ordering
of receipt timing which is notified by the memory-
mapped peripheral resources through the method
except bus when the register is changed by bus
accesses. Refer to the description of each registers to
guarantee this ordering.

Renesas SuperH SH-4A Specifications

General

Brand	Renesas
Model	SuperH SH-4A
Category	Computer Hardware
Language	English