Rev. 1.50, 10/04, page 443 of 448
Item Page Revision (See Manual for Details)
10.1.76 SYNCO (Synchronize
Data Operation)
• Example
333 Deleted.
1. Ordering access to memory areas which are shared
with other memory users
2. Ordering access to memory-mapped hardware
registers
2. Flushing all write buffers
3. Stopping memory-access operations from merging
and becoming ineffective
4. Waiting for the completion of cache-control
instructions
10.1.77 TAS (Test And Set):
Logical Instruction
• Possible Exceptions
335 Amended.
Exceptions are checked taking a data access by this
instruction as a byte load and a byte store.
10.1.79 TST (Test Logical)
• Possible Exceptions
338 Added.
Exceptions are checked taking a data access by this
instruction as a byte load and a byte store.
10.1.80 XOR (Exclusive OR
Logical)
• Possible Exceptions
340 Added.
Exceptions are checked taking a data access by this
instruction as a byte load and a byte store.
10.3.19 FSCA (Floating Point
Sine And Cosine Approximate)
• Description
408 Amended.
(absolute error is within ±2^–21)
10.3.22 FSRRA (Floating Point
Square Reciprocal Approximate)
• Description
414 Added.
This instruction takes the approximate inverse of the
arithmetic square root (absolute error is within ±2^–21)
of the single-precision floating-point in FRn and writes
the result to FRn.
Section 11 List of Registers
• Register Addresses (by
functional module, in order of
the corresponding section
numbers)
427 Deleted.
• Descriptions by functional module, in order of the
corresponding section numbers
• Access to reserved addresses which are not described in
this list is disabled.
• When registers consist of 16 or 32 bits, the addresses of
the MSBs are given, on the presumption of a big-endian
system.
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