Renesas SuperH SH-4A User Manual

Rev. 1.50, 10/04, page 444 of 448
Item Page Revision (See Manual for Details)
431 Added.
The write value to the reserved bits should be the initial
value.
The operation is not guaranteed if the write value is not
the initial value.
The CPUOPM register should be updated by the CPU
store instruction not the access from SuperHyway bus
master except CPU.
After the CPUOPM is updated, read CPUOPM once,
and execute one of the following two methods.
1. Execute a branch using the RTE instruction.
2. Execute the ICBI instruction for any address
(including non-cacheable area).
After one of these methods are executed, it is
guaranteed that the CPU runs under the updated
CPUOPM value.
Appendix A
432 Amended.
Bit
Bit
Name
Initial
Value R/W Description
31 to
6
 H'000000F R Reserved
The write value must be the initial value.
5 RABD 1 R/W Speculative execution bit for subroutine return
0: Instruction fetch for subroutine return is issued
speculatively. When this bit is set to 0, refer to
Appendix C, Speculative Execution for Subroutine
Return.
1: Instruction fetch for subroutine return is not issued
speculatively.
4  0 R Reserved
The write value must be the initial value.
3 INTM
U
0 R/W Interrupt mode switch bit
0: SR.IMASK is not changed when an interrupt is
accepted.
1: SR.IMASK is changed to the accepted interrupt
level.
2 to 0  All 0 R Reserved
The write value must be the initial value.
Appendix C. Speculative
Execution for Subroutine Return
434 Added.
Appendix D Version Registers
(PVR, PRR)
435,
436
Added.

Renesas SuperH SH-4A Specifications

General

Brand	Renesas
Model	SuperH SH-4A
Category	Computer Hardware
Language	English