Renesas SuperH SH-4A

Rev. 1.50, 10/04, page 39 of 448
Instruction Operation Instruction Code Privileged T Bit New
STC VBR,Rn VBR → Rn 0000nnnn00100010 Privileged — —
STC SSR,Rn SSR → Rn 0000nnnn00110010 Privileged — —
STC SPC,Rn SPC → Rn 0000nnnn01000010 Privileged — —
STC SGR,Rn SGR → Rn 0000nnnn00111010 Privileged — —
STC DBR,Rn DBR → Rn
0000nnnn11111010
Privileged — —
STC Rm_BANK,Rn Rm_BANK → Rn
(m = 0 to 7)
0000nnnn1mmm0010
Privileged — —
STC.L SR,@-Rn Rn – 4 → Rn, SR → (Rn)
0100nnnn00000011
Privileged — —
STC.L GBR,@-Rn Rn – 4 → Rn, GBR → (Rn)
0100nnnn00010011
— — —
STC.L VBR,@-Rn Rn – 4 → Rn, VBR → (Rn)
0100nnnn00100011
Privileged — —
STC.L SSR,@-Rn Rn – 4 → Rn, SSR → (Rn)
0100nnnn00110011
Privileged — —
STC.L SPC,@-Rn Rn – 4 → Rn, SPC → (Rn)
0100nnnn01000011
Privileged — —
STC.L SGR,@-Rn Rn – 4 → Rn, SGR → (Rn)
0100nnnn00110010
Privileged — —
STC.L DBR,@-Rn Rn – 4 → Rn, DBR → (Rn)
0100nnnn11110010
Privileged — —
STC.L Rm_BANK,@-Rn Rn – 4 → Rn,
Rm_BANK → (Rn)
(m = 0 to 7)
0100nnnn1mmm0011
Privileged — —
STS MACH,Rn MACH → Rn
0000nnnn00001010
— — —
STS MACL,Rn MACL → Rn
0000nnnn00011010
— — —
STS PR,Rn PR → Rn
0000nnnn00101010
— — —
STS.L MACH,@-Rn Rn – 4 → Rn, MACH → (Rn)
0100nnnn00000010
— — —
STS.L MACL,@-Rn Rn – 4 → Rn, MACL → (Rn)
0100nnnn00010010
— — —
STS.L PR,@-Rn Rn – 4 → Rn, PR → (Rn)
0100nnnn00100010
— — —
SYNCO Prevents the next instruction
from being issued until
instructions issued before
this instruction have been
completed.
0000000010101011
  New
TRAPA #imm PC + 2 → SPC,
SR → SSR, #imm << 2 → TRA,
H'160 → EXPEVT,
VBR + H'0100 → PC
11000011iiiiiiii
— — —