RFL 9300 RFL Electronics Inc.
August 9, 2001 4 - 6 (973) 334-3100
4.2.5 DLAY SEC - TIME DELAY
Parameter #24 (DLAY SEC) is a time delay setting that controls two RFL 9300 functions: bias
control (parameter #22) and ground delay (parameter #23). The following settings are available:
Setting Bias Control Ground Delay
.05/.05 50 ms 50 ms
.1/.1 100 ms 100 ms
.15/.15 150 ms 150 ms
.2/.2 200 ms 200 ms
.25/.25 250 ms 250 ms
.3/.3 300 ms 300 ms
.35/.35 350 ms 350 ms
.4/.4 400 ms 400 ms
.45/.45 450 ms 450 ms
.5/.5 500 ms 500 ms
.55/.55 550 ms 550 ms
.6/.6 600 ms 600 ms
.65/.65 650 ms 650 ms
.7/.7 700 ms 700 ms
.75/.75 750 ms 750 ms
.8/2 800 ms 2 s
.85/5 850 ms 5 s
.9/10 900 ms 10 s
.95/15 950 ms 15 s
1/30 1000 ms 30 s
Bias control provides security during capacitive inrush current. Ground delay provides security
during inductive inrush current (such as for a low-side fault on a tapped line). Since both are “in-
rush” events, a common timer is used.
Most applications will not require trip suppression for either inrush condition. This means that
bias control and ground delay will both be disabled. If they are both disabled, the time delay set-
ting will have no effect on RFL 9300 performance.
If either bias control or ground delay parameters are enabled, the time delay setting should be
made long enough to override the inrush condition, plus a safety margin.
As of the date this manual was published, no guidelines have been established for those rare
applications where a time delay setting must be made. These are unusual cases that are com-
pletely dependent on the parameters of the power system. Field measurements, EMTP-type
studies, or TNA studies may be required on a case-by-case basis to determine the proper set-
ting.
If the ground delay parameter is enabled specifically for the purpose of enabling the 3IO single-
pole trip algorithm it is recommended that a setting of 50ms be used. Keep in mind that the
ground delay timer does not start until the time a 3IO trip signal would have been issued in a
three-pole application. This means that with a 50ms setting the timer may not expire until as
much as 80 to 90ms after the fault. Remember that trip signals are calculated at the conclusion
of positive half-cycles of line current. Should a positive half-cycle terminate just prior to the 50ms
time-out it will be an additional 16ms before the 3IO trip will be transmitted to the 93B SV which
must then pass the trip command to the phase controllers.
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