RFL 9300 RFL Electronics Inc.
October 29, 2001 10 - 3 (973) 334-3100
10.3 THEORY OF OPERATION
The RFL 93 SV Supervisor Controller Module serves as the communications hub of the RFL 9300. It also per-
forms the following tasks:
1. It generates the system clock, which is the "heartbeat" of all RFL 9300 activity.
2. It controls the initialization of all modules in the RFL 9300 during turn-on.
3. It monitors and controls many system-wide functions, such as alarms, Direct Transfer Trip (DTT) sig-
nals, reclose block signals, and the single-pole trip algorithms.
4. It works hand-in-hand with the Display Controller to both initialize the single-pole chassis and to monitor
the serial link between the single-pole chassis and the RFL 9300. (See 9.2.3 - Single-Pole Interfacing -
for an explanation of this process).
10.3.1 SYSTEM CLOCK
Timer 2, an on-board software timer, is programmed to generate the system clock. The Supervisor Controller
checks jumper J1's setting to determine the desired clock frequency. If J1 is set for 50-Hz operation, a 1.667-
kHz system clock signal will be generated. If J1 is set for 60-Hz operation, system, a 2-kHz clock signal will be
generated. If the relay is configured for 3-terminal operation, the system clock is phase locked at 33 x the line
frequency in Hz. The clock signal is output on the HS0.0 pin, and is transmitted to the Phase Controllers, com-
munications controllers, and single-pole logic through U3-3. This clock signal is used to synchronize the Phase
Controller, communications controller, single-pole logic and Supervisor Controller programs.
10.3.2 INTERBOARD COMMUNICATIONS MANAGEMENT
The primary task of the RFL 93B SV is to control the flow of messages between the RFL 93B PC Phase Con-
troller Modules, the RFL 93B Display Controller Module, and the RFL 93B CC Communications Controller Mod-
ule. The Supervisor Controller algorithms are executed by 16-bit microcontroller U9. U9's 16-MHz clock signal is
generated by an on-board clock oscillator, controlled by crystal Y1 and capacitors C33 and C34.
The RFL 93B PC Phase Controller Modules and the RFL 93B CC Communications Controller Module do not
communicate directly with the RFL 93B SV, or with each other. These three controllers use a non-volatile static
RAM (U25) for this purpose. Each controller is assigned two "mailboxes" within U25: READ and WRITE. Each
mail-box contains eight bytes, but only the first three are presently used. Messages passed between controllers
all have the same three-byte format: an address byte, a data byte, and a security code byte. The security code
byte is calculated as the "XOR" of the address and data bytes. All three bytes are stored in the appropriate mail-
box.
At the start of each 0.5-ms program interval, the RFL 93B SV will write whatever messages it has available for a
given controller to that controllers' READ mailbox in U25. U25 is treated as memory-mapped I/O. Whenever the
target memory address is greater than or equal to 8000H (AD15 = logic 1), a memory-mapped I/O operation
occurs. When this signal is high, EPROMS U14 and U15 are disabled by their Chip Select line. This signal is
also inverted by U10A and applied to the READY/BUSWIDTH input pins of the microcontroller, with the follow-
ing results:
1. The RFL 93B SV treats all memory-mapped I/O bus cycles as eight-bit operations.
2. Two wait states are inserted into each memory-mapped I/O bus cycle to accommodate U25's rather
slow 200-ns access time
When the RFL 93B SV wants to write to the mailboxes, the following events take place:
1. The SUPR/W signal (U3-12) is set to a logic 1. This gives the RFL 93B SV's WR, RAM, and RD control
signals access to U25 through multiplexer U24. At the same time, buffer U23's outputs are disabled; this
isolates U25 from the external controller strobe signals. The MEMADDR output signal from PLD U20-14
goes low to enable address latch U19.
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