RFL 9300 RFL Electronics Inc.
October 29, 2001 10 - 4 (973) 334-3100
2. The PCR/WEN signal (U3-7) is set to a logic 1. This signal clears INT-X address counter U28A to the
INT-A address (000), and disables INT-X address decoder device U30. The memory access control
timer U29 is disabled by the PLDs TIMEREN signal (U20-13).
3. The COMM_EN signal (U3-9) is set to a logic 1 to isolate the RFL 93B CC module (or modules) from
U25.
At the start of the I/O bus cycle, the target address appears on the microcontroller pins AD15 to AD0 (U9-45
through U9-60), and on the outputs of address latches U12 and U13. When ALE goes low, the target address
remains latched on the output pins of these devices. The low READY/BUSWIDTH signal on U10-1 also enables
decoder device U11B. SUPR/W is the B address signal for this decoder, while AD14 is the A address signal.
Therefore, if AD14 is a logic zero, U11-10 will be low. This does two things: U11A is enabled, and the RAM sig-
nal goes low.
The RAM signal serves as the Chip Enable signal for U25. If AD13 is low during a bus cycle, address line
ADR100 will go low and provide one enable signal to U17. When the RD signal goes low, U25's outputs will be
enabled and the data from the memory location addressed by U19 will appear on the bi-directional data bus and
the input of U17. The low RD signal provides the remaining enable signal required by U17 and enables the
memory data to appear on its output pins and be read by microcontroller U9. Memory address 8XXXH is used
for memory-mapped I/O mailbox READ cycles, and memory address AXXXH is used for mailbox WRITE cycles.
U10B decodes a WRITE strobe (the WRSTRB signal) for bi-directional data bus latch U18. Memory address
CXXXH will enable the Output Control latch (U16) to be accessed through U10C, U10D, and the ADR110 sig-
nal.
After the RFL 93B SV is finished writing data to the mailbox registers, it grants the phase controllers access to
the memory. The SUPR/W signal is reset to logic zero. This enables the outputs of input buffer U23, allowing
externally-generated strobe signals access to U25 through multiplexer U24. The PCR/WEN signal is also reset
to logic zero. This enables U28A along with INT-X decoder U30. U28A supplies the interrupt address to decoder
U30. When the PCR/WEN signal first goes low the address supplied to U30 by U28A will be "000." U30 will de-
code this signal and generate a communications interrupt signal to the Phase A controller through the INT-A
signal. The TIMERSTR signal from the PLD (U20-17) disables U30's input address lines when U28A is clocked
by the BLKADDR signal (U20-16). This prevents glitches on the output of U30 that would provide false interrupt
signals to the phase controllers. U29, a 45 μs memory access control timer, is also started. This timer insures
that a non-responsive or disabled phase controller does not use more than its share of mailbox access time. If
U29 times out, it will signal counter U28A to address the next phase controller. U30 will decode the new ad-
dress and redirect the INT-X signal to the addressed phase controller. The offending phase controller will then
be disconnected from the mailbox.
The external controller modules use one of the 4-bit binary counters in U28 (U28B) to address their mailbox lo-
cations in the non-volatile static RAM. U28B provides the three least-significant bits of the address. This counter
is advanced by the ADDRCLK signal supplied by the PLD (U20-18). Whenever the external RD signal goes
high, the address is advanced. Higher order address bits are supplied by the outputs of U28A and programma-
ble logic array U20.
The external WRITE DATA EN strobe provides the address bit that determines whether access is granted to a
read or write mailbox location. This signal also provides the direction control for bi-directional data bus trans-
ceiver U27. The COMM2-ADDR signal determines which communications controller mailbox is being ad-
dressed. If COMM2-ADDR is at logic one, the mailbox for Communications Controller #1 is addressed; the other
mailbox is addressed when COMM2-ADDR is at logic zero.
At the end of the mailbox access routine, each phase controller will toggle its RD and WR strobes simultane-
ously to re-start the access control timer through U20-17. At the same time, the BLKADDR signal (U20-16) will
be issued to advance the interrupt signal to the next phase controller. When all phase controllers have had ac-
cess to their mailboxes during the current 0.5-ms program interval, U28A-5 will go high. The access control
timer will be disabled and the SUPER_RD interrupt signal will be issued to the Supervisor Controller. The Su-
pervisor Controller will respond by once again setting SUPR/W high, isolating the external controller modules
from the mailbox memory.
To Next Page
Loading...