RFL 9300 RFL Electronics Inc.
October 29, 2001 10 - 5 (973) 334-3100
The Supervisor Controller will then read the messages passed by the phase and communications controllers.
After all mailbox registers have been read, the Supervisor Controller will reset the SUPR/W line and issue a low
COMM_EN (U3-9) signal. This will enable the Communications Controller to access the mailbox memory. The
Communications Controller will maintain access to the mailbox memory for the rest of the 0.5-ms program inter-
val. The Supervisor Controller will use this time to process the data it has received from the other controllers,
and to perform the other tasks assigned to it.
Program instructions are accessed whenever the target address is less than 8000H during external bus cycles.
The READY/BUSWIDTH signal will be high, indicating a 16-bit bus operation with no wait states. With AD15
low, EPROM's U14 and U15 will be enabled; these devices hold the program instructions. Output address de-
coder U11 will be disabled through U10-1. This insures that the internal microcontroller data bus will be isolated
from the memory-mapped I/O bi-directional data bus. During these intervals, the non-volatile static RAM is
made available to the phase and communications controllers.
10.3.3 OUTPUT CONTROL LATCH
D-type flip-flop U16 serves as the output control latch, accessed through address CXXX. U16 provides the fol-
lowing signals to the phase controllers:
Signal
Pin No.
A SUP EN U16-19
B SUP EN U16-18
C SUP EN U16-17
G SUP EN U16-16
A logic high on any of these lines will disable trip on the corresponding phase controller. The phase controller
has the ability to override this disable signal if it enters the back-up mode and forces its BACK-UP EN signal
low. If the Supervisor Controller resets, it will drive these lines high and disable all phase controller trip signals.
The Supervisor Controller has the ability to access any memory location within static RAM U25, not just the
mailbox locations. U16-12, U16-13 and U16-14 provide the three most-significant address bits to U25. These
signals give the Supervisor Controller the ability to address the upper 1792 bytes of memory within U25. The
external controllers have the ability to access only their mailbox registers.
10.3.4 SERIAL COMMUNICATIONS LINK WITH DISPLAY CONTROLLER
The Supervisor Controller communicates with the display controller through its serial port (U9-18 and U9-17).
This serial link uses RS-485 transceiver U2, along with the SC READY (U16-15) and DC RDY (U1-4) control
lines. Serial data is transmitted and received over the SERIAL I/O + and SERIAL I/O - signal lines. The
PORT1.7 signal is used to control the transmit/receive status of U2.
A logic low signal on SC READY indicates that the RFL 93B SV is ready to receive serial data from the display
controller in the RFL 93B DISPLAY. A logic high signals the display controller not to transmit. This signal pro-
vides a hardware enable/disable signal to the RS-485 transceiver located on the display controller board.
The DC RDY signal is supplied by the display controller. If this signal is a logic one, the display controller is not
ready to communicate with the RFL 93B SV.
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