RFL 9300 RFL Electronics Inc.
October 29, 2001 10 - 7 (973) 334-3100
3I0 Trip Algorithm - When the RFL 9300 relay is configured for single-pole operation the GROUND DELAY func-
tion takes on an additional role. If GROUND DELAY is not enabled, trips calculated by the 3I0 controller will
have no effect. In certain applications, such as tapped loads, the ground bias may be set much more sensitive
than the phase bias and only a 3I0 trip signal will be available to clear low-level internal faults. In this case
GROUND DELAY must be enabled to insure that there will be adequate time to allow the individual Phase Con-
trollers to trip their breakers. Then, when the 93B SV receives a trip signal from the 3I0 controller, if none of the
Phase Controllers has issued a trip signal all three will be commanded to trip since the 3I0 controller can’t pass
its trip signal to the 93B SV unless the programmed GROUND DELAY has already expired.
When GROUND DELAY is enabled specifically for the purpose of allowing 3I0 single-pole trips it is recom-
mended that a setting of 50ms be used. Keep in mind that the ground delay timer doesn’t start until a 3I0 trip
signal would have been issued in a three-pole application i.e. after the normal 3I0 trip delay. This means that
with a 50ms setting the timer may not expire until as much as 80 to 90ms after the fault. Remember that trip
signals are calculated at the conclusion of positive half-cycles of line current. Should a positive half-cycle termi-
nate just prior to the 50ms time-out it will be an additional 16ms before the 3I0 trip will be passed to the 93B SV
which must then pass the trip command to the phase controllers.
10.3.7 JUMPERS, ALARMS, WATCHDOG TIMER, AND POWER SUPPLY SUPERVISOR
Jumpers J1, J2 and J3 are used to configure the CCS system as follows:
J1 Position A for a 60-Hz system.
Position B for a 50-Hz system.
J2 Position C for a two-terminal configuration.
Position D for a three-terminal configuration.
J3 Position E for a 5A rms system.
Position F for a 1A rms system.
J4 Position J is used for 64K EPROM memory devices (U14 and U15). In this position pin 27 is connected
to +5Vdc. For a 64K EPROM with the standard JEDEC footprint, pin 27 is the programming pin. Jumper
position K is used for 256K EPROM memory devices. For a 256K EPROM with the standard JEDEC
footprint pin 27 is address bit A14. In this circuit this address pin is grounded to limit access to the lower
128K of EPROM memory.
J5 Position G for 3-pole tripping.
Position H for single pole tripping. (See Section 24 for more information on single pole tripping)
The jumper status signals and the BACK-UP EN signal received from the other phase controllers are read
through the 1A inputs of U5. All of the phase controllers share the BACK-UP EN signal line through an open
collector inverter. This line will be pulled low if only one of the phase controllers enters back-up mode. In a nor-
mal situation, this can't happen because the phase controllers will either all enter back-up mode or none of them
will. The 1Y and 2Y outputs share the PORT0.0 - PORT0.3 inputs of the microcontroller. The jumper signals
and the BACK-UP EN signal are available on this 4-bit bus whenever the PORT1.0 signal is a logic 1. When this
signal is a logic 0 the alarm signals from the phase controllers are available on the bus.
The PORT1.0 signal is the watchdog timer strobe pulse. Each time this signal goes high the 1500 μs watchdog
timer (U7) is restarted and the jumper settings (J1, J2 and J3) and back-up status inputs are read. After this sig-
nal is brought low the phase controller alarm input signals are read. The alarm signals are active high.
If the first stage of the watchdog timer is not pulsed within about 1530 μs, it will time out and the B input of the
second stage will be pulsed. This will cause a 30 μs reset pulse to be applied to the microcontroller through U6-
5. The watchdog timer strobe pulse is also applied to U6-6. In the event that the microcontroller stops strobing
the watchdog timer, a counter-driven watchdog timer inside power supply supervisor U6 will time out and deliver
a 50 ms reset pulse to the microcontroller. This acts as a back-up to the main watchdog timer. In addition to pro-
viding a back-up watchdog timer function, the power supply supervisor provides a 50-ms reset pulse any time
the power supply voltage drops below 4.5 Vdc. This guarantees a reset pulse to the microcontroller if a "brown-
out" condition occurs.
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