RFL 9300 RFL Electronics Inc.
March 26, 1999 12 - 3 (973) 334-3100
TP5 Monitoring point for a copy of the low-going INT-X signal on edge connector terminal P1-A6;
this signals a communications interrupt request. This signal will go low about 45 ms after the
leading edge of the system clock signal.
The phase controller has access to the non-volatile static RAM mailbox memory chip on the
RFL 93B SV Supervisor Controller Module whenever this signal is low. It is derived from a one
shot timer on the Supervisor Controller, and should never last for more than about 50 ms. The
strobe signals on edge connector terminals P1-A24, P1-A25, P1-C24, and P1-C25 are active
only when this signal is low. They are in tri-state mode at all other times.
TP6 8-MHz clock signal. The system clock signal is divided by two within the microcontroller.
TP7 Monitoring point for AUX IN signal.
TP8 Monitoring point for 5-volt reference voltage.
12.3 THEORY OF OPERATION
The RFL 9300's protection algorithms are executed by U9, a 16-bit microcontroller. Timers inside U9 are pro-
grammed to monitor the system clock signal supplied by the Supervisor Controller through edge connector ter-
minal P1-C11. When the relay is configured for 2-terminal operation the period of the clock signal must remain
between 498μs and 502μs (598μs and 602μs for 50-Hz systems). If the period goes beyond these limits, U9 will
reset. When the relay is configured for 3-terminal operation, the system clock is phase locked to the line current
at a frequency equal to 33 times the line frequency in Hz. Write or read operations from address locations of
8000H or higher will result in a low signal on pins U9-43 and U9-64 through NAND gate U10. This causes U9 to
switch to its 8-bit external bus mode and to insert a 125 ns wait state into the bus cycle.
The microcontrollers' internal clock signal is provided by an on-board gate oscillator. Crystal Y1 and capacitors
C26 and C27 are the frequency-determining components for this oscillator.
An external microcontroller bus cycle utilizes the WR, RD, and ALE signals. Instructions and data are read from
EPROM's U14 and U15, while octal flip-flops U18 and U20, octal latch U19, and shift register U21 serve as
memory-mapped I/O ports.
At the start of the external bus cycle, the three control signals are high. The ALE signal provides a high latch
control signal to latch the address bits into U12 and U13, which serve as a memory address buffer. The external
target address appearing on lines AD0 through AD15 also appears on the buffer output pins. When the ALE
signal goes low the address remains latched on the buffer outputs.
The RD signal (U9-61) serves as the output enable signal for EPROM's U14 and U15, the read address de-
coder section of U11, and buffer/driver U17. If the memory address is less than 8000H, AD15 is low. This
serves as the EPROM chip select and enables 16-bit program instruction words to be read by U9. If U9 is exe-
cuting a byte operation, the unwanted 8-bit portion of the 16-bit word is discarded. Also, when AD15 is low,
buffers U16 and U17 will be tri-stated, and the external memory-mapped I/O ports (U18 through U21) will be
isolated from the microcontroller bus.
Memory-mapped I/O bus cycles differ from instruction fetch I/O bus cycles in several respects:
1. The width of the data bus is dynamically altered from 16 bits to 8 bits.
2. Both read and write bus cycles take place.
3. Memory-mapped I/O bus cycles are mapped at memory addresses 8000H and above (line AD15 high).
4. A 125-ns wait state is inserted into the bus cycle.
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