RFL 9300 RFL Electronics Inc.
March 26, 1999 12 - 4 (973) 334-3100
When the address is 8000H or higher, the EPROMS are disabled. At the same time, U10-8 (which provides the
ready/buswidth signal) is low. This configures the data bus as an 8-bit bus, and the bus cycle is extended by
one wait state. This signal also enables the Y0 and Y1 outputs on both halves of memory-mapped I/O decoder
U11 in conjunction with the microcontroller RD and WR signals, depending on the desired type of bus cycle.
U11-1 through U11-7 form the read decoder section, and U11-9 through U11-16 form the write decoder section.
The phase controller can pass messages to and from the mailbox on the Supervisor Controller (Section 10)
when the INT-X signal (edge connector terminal P1-A6) goes low. The low-going leading edge of this signal is
inverted by U2 and generates the microcontroller communications interrupt signal. The external strobes re-
quired to access the mailbox are enabled through buffer/line driver U3 when this signal is low. The strobe sig-
nals are RD (edge connector terminal P1-A24), WR (P1-A25), CS (P1-C24), and WRITE DATA EN (P1-C25).
Messages being sent to the Supervisor Controller are latched into octal flip-flop U18. Messages are read from
the Supervisor Controller through octal latch U19. Address 8000H, decoded by U11, is used for both of these
buffers. The Supervisor Controller has an on-board timer that monitors the INT-X signal. The Phase Controller is
allowed 50μs to complete the mailbox access before the Supervisor Controller will pull INT-X high, disabling all
strobe lines.
Address 8001H is also decoded by U11. It is used to access buffers U20 and U21. Phase current waveform
data is supplied by the ACT I/O module through edge connector terminal P1-A32. Operational amplifier U26 and
analog switch U25 are used in a range-switching scheme that makes 8-bit serial A/D converter U22 appear to
provide an equivalent 10-bit conversion (9 bits plus sign). The 2.5-V
peak
full-scale signal received from the ACT
I/O module is equivalent to 15.875 A
peak
. Operational amplifier U24 amplifies this by two to bring the full-scale
signal level to 5 volts. Voltage reference U23 supplies a precise 5-volt dc reference to A/D converter U22. The
input to the A/D converter (U22-2) will be at 2.5 volts when the ACT I/O output is zero. As the ACT I/O signal
covers its full range (+5 volts to –5 volts), the A/D converter's input signal will range from +5 volts to zero. U22
converts this unipolar input to a bipolar output using an offset binary code.
Microcontroller U9 uses the A/D CHIP SEL and A/D CLOCK signals to serially convert the analog signal to a
digital value and latch the result into buffer chip U21. The A/D CLOCK is an 8-cycle 1-MHz clock signal, gener-
ated by using the microcontrollers' serial port in the synchronous mode. The eighth clock pulse starts a new
conversion, and it is this value that will be read during the following 0.5-ms interval. Because of this, the value
read by the microcontroller is always 0.5 ms old. If the peak CT current exceeds 14 amperes, analog switch
U25 will be commanded to switch channels and the input signal will be supplied through U26. This effectively
reduces the gain by a factor of 4, allowing the maximum level of the ACT I/O output to increase to 63.5 A
peak
.
When operating in this mode the resolution of the A/D converter's least-significant bit is reduced by a factor of 4
from 1/8 ampere to ½ ampere. Diodes CR1 and CR2 and resistor R21 protect U22 against negative input signal
levels.
The front-panel ALARM and FD indicators are accessed through output buffer U21. Additional signals supplied
by this buffer are L1.5 EN and L3A EN OUT. These two signals are part of the loss-of-load hardware bus that
runs between all phase controller modules. L1.5 EN is low when phase CT current is 1.5 A
rms
or more. L3A EN
OUT is high when phase CT current is 3 A
rms
or more. This signal is inverted by an open-collector inverter in
U2 (U2-8 out), and pulls down the 3 ampere loss-of-load signal line (R3A EN IN) when the CT current is 3 A
rms
or more.
Additional loss-of-load function signals are received from the other phase controller modules through octal
buffer U1. They are R1.5 EN1, R1.5 EN2 and R3A EN IN. These are the 1.5 ampere and 3 ampere remote sig-
nals required for the loss-of-load function. If any phase current exceeds 3 A
rms
, the R3A EN IN line will be
pulled low. This backup function has the capability of operating even if the Supervisor Controller can't communi-
cate with the phase controller modules. U20 also supplies the ACT gain range switch signals mentioned above.
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