UM0306 Advanced control timer (TIM1)
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Bits 6:4
OC1M: Output Compare 1 Mode.
These bits define the behavior of the output reference signal OC1REF from which
OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active
level depends on CC1P and CC1NP bits.
000: Frozen - The comparison between the output compare register TIM1_CCR1 and
the counter TIM1_CNT has no effect on the outputs.
001: Set channel 1 to active level on match. OC1REF signal is forced high when the
counter TIM1_CNT matches the capture/compare register 1 (TIM1_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIM1_CNT matches the capture/compare register 1 (TIM1_CCR1).
011: Toggle - OC1REF toggles when TIM1_CNT=TIM1_CCR1.
100: Force inactive level - OC1REF is forced low.
101: Force active level - OC1REF is forced high.
110: PWM mode 1 - In up-counting, channel 1 is active as long as
TIM1_CNT<TIM1_CCR1 else inactive. In down-counting, channel 1 is inactive
(OC1REF=‘0’) as long as TIM1_CNT>TIM1_CCR1 else active (OC1REF=’1’).
111: PWM mode 2 - In up-counting, channel 1 is inactive as long as
TIM1_CNT<TIM1_CCR1 else active. In down-counting, channel 1 is active as long
as TIM1_CNT>TIM1_CCR1 else inactive.
Note 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIM1_BDTR register) and CC1S=’00’ (the channel is configured in
output).
Note 2: In PWM mode 1 or 2, the OCREF level changes only when the result of the
comparison changes or when the output compare mode switches from “frozen” mode
to “PWM” mode.
Bit 3
OC1PE: Output Compare 1 Preload enable.
0: Preload register on TIM1_CCR1 disabled. TIM1_CCR1 can be written at anytime,
the new value is taken in account immediately.
1: Preload register on TIM1_CCR1 enabled. Read/Write operations access the
preload register. TIM1_CCR1 preload value is loaded in the active register at each
update event.
Note 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIM1_BDTR register) and CC1S=’00’ (the channel is configured in
output).
Note 2: The PWM mode can be used without validating the preload register only in one
pulse mode (OPM bit set in TIM1_CR1 register). Else the behavior is not guaranteed.
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