Advanced control timer (TIM1) UM0306
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Input capture mode
Bit 2
OC1FE: Output Compare 1 Fast enable.
This bit is used to accelerate the effect of an event on the trigger in input on the CC
output.
0: CC1 behaves normally depending on counter and CCR1 values even when the
trigger is ON. The minimum delay to activate CC1 output when an edge occurs on
the trigger input is 5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output.
Then, OC is set to the compare level independently from the result of the
comparison. Delay to sample the trigger input and to activate CC1 output is reduced
to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2
mode.
Bits 1:0
CC1S: Capture/Compare 1 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used
input.
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.
10: CC1 channel is configured as input, IC1 is mapped on TI2.
11: CC1 channel is configured as input, IC1 is mapped on TRGI. This mode is
working only if an internal trigger input is selected through TS bit (TIM1_SMCR
register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ’0’ in
TIM1_CCER).
Bits 15:12 IC2F: Input Capture 2 Filter.
Bits 11:10 IC2PSC[1:0]: Input Capture 2 Prescaler.
Bits 9:8
CC2S: Capture/Compare 2 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used
input.
00: CC2 channel is configured as output.
01: CC2 channel is configured as input, IC2 is mapped on TI2.
10: CC2 channel is configured as input, IC2 is mapped on TI1.
11: CC2 channel is configured as input, IC2 is mapped on TRGI. This mode is
working only if an internal trigger input is selected through TS bit (TIM1_SMCR
register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = ’0’ in
TIM1_CCER).