UM0306 Controller area network (bxCAN)
309/519
CAN receive FIFO 1 register (CAN_RF1R)
Address Offset: 10h
Reset value: 00h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
1514131211109876543210
Reserved
RFOM1 FOVR1 FULL1 Res. FMP1[1:0]
rs rc_w1 rc_w1 r r
Bits 31:6 Reserved, forced by hardware to 0.
Bit 5
RFOM1: Release FIFO 1 Output Mailbox
Set by software to release the output mailbox of the FIFO. The output mailbox can
only be released when at least one message is pending in the FIFO. Setting this
bit when the FIFO is empty has no effect. If at least two messages are pending in
the FIFO, the software has to release the output mailbox to access the next
message.
Cleared by hardware when the output mailbox has been released.
Bit 4
FOVR1: FIFO 1 Overrun
This bit is set by hardware when a new message has been received and passed
the filter while the FIFO was full.
This bit is cleared by software.
Bit 3
FULL1: FIFO 1 Full
Set by hardware when three messages are stored in the FIFO.
This bit is cleared by software.
Bit 2 Reserved, forced by hardware to 0.
Bits 1:0
FMP1[1:0]: FIFO 1 Message Pending
These bits indicate how many messages are pending in the receive FIFO1.
FMP1 is increased each time the hardware stores a new message in to the FIFO1.
FMP is decreased each time the software releases the output mailbox by setting
the RFOM1 bit.
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