Controller area network (bxCAN) UM0306
310/519
CAN interrupt enable register (CAN_IER)
Address Offset: 14h
Reset value: 00h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved SLKIE WKUIE
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ERRIE Reserved
LEC
IE
BOF
IE
EPV
IE
EWG
IE
Res.
FOV
IE1
FF
IE1
FMP
IE1
FOV
IE0
FF
IE0
FMP
IE0
TME
IE
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:18 Reserved, forced by hardware to 0.
Bit 17
SLKIE: SLEEP Interrupt Enable
0: No interrupt when SLAKI bit is set.
1: Interrupt generated when SLAKI bit is set.
Bit 16
WKUIE: Wake-Up Interrupt Enable
0: No interrupt when WKUI is set.
1: Interrupt generated when WKUI bit is set.
Bit 15
ERRIE: Error Interrupt Enable
0: No interrupt will be generated when an error condition is pending in the
CAN_ESR.
1: An interrupt will be generation when an error condition is pending in the
CAN_ESR.
Bits 14:12 Reserved, forced by hardware to 0.
Bit 11
LECIE: Last Error Code Interrupt Enable
0: ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on
error detection.
1: ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error
detection.
Bit 10
BOFIE: Bus-Off Interrupt Enable
0: ERRI bit will not be set when BOFF is set.
1: ERRI bit will be set when BOFF is set.
Bit 9
EPVIE: Error Passive Interrupt Enable
0: ERRI bit will not be set when EPVF is set.
1: ERRI bit will be set when EPVF is set.
Bit 8
EWGIE: Error Warning Interrupt Enable
0: ERRI bit will not be set when EWGF is set.
1: ERRI bit will be set when EWGF is set.
Bit 7 Reserved, forced by hardware to 0.
Bit 6
FOVIE1: FIFO Overrun Interrupt Enable
0: No interrupt when FOVR is set.
1: Interrupt generation when FOVR is set.
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