Controller area network (bxCAN) UM0306
312/519
CAN error status register (CAN_ESR)
Address Offset: 18h
Reset value: 00h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REC[7:0] TEC[7:0]
rrrrrrrrrrrrrrrr
1514131211109876543210
Reserved LEC[2:0] Res. BOFF EPVF EWGF
rw rw rw r r r
Bits 31:24
REC[7:0]: Receive Error Counter
The implementing part of the fault confinement mechanism of the CAN protocol. In
case of an error during reception, this counter is incremented by 1 or by 8
depending on the error condition as defined by the CAN standard. After every
successful reception the counter is decremented by 1 or reset to 120 if its value
was higher than 128. When the counter value exceeds 127, the CAN controller
enters the error passive state.
Bits 23:16
TEC[7:0]: least significant byte of the 9-bit Transmit Error Counter
The implementing part of the fault confinement mechanism of the CAN protocol.
Bits 15:7 Reserved, forced by hardware to 0.
Bits 6:4
LEC[2:0]: Last Error Code
This field is set by hardware and holds a code which indicates the error condition
of the last error detected on the CAN bus. If a message has been transferred
(reception or transmission) without error, this field will be cleared to ‘0’.
Code 7 is unused and may be written by the hardware to check for an update
000: No Error
001: Stuff Error
010: Form Error
011: Acknowledgment Error
100: Bit recessive Error
101: Bit dominant Error
110: CRC Error
111: Set by software
Bit 3 Reserved, forced by hardware to 0.
Bit 2
BOFF: Bus-Off Flag
This bit is set by hardware when it enters the bus-off state. The bus-off state is
entered on TEC overflow, greater than 255, refer to Section 14.5.6 on page 296.
Bit 1
EPVF: Error Passive Flag
This bit is set by hardware when the Error Passive limit has been reached
(Receive Error Counter or Transmit Error Counter>127).
Bit 0
EWGF: Error Warning Flag
This bit is set by hardware when the warning limit has been reached
(Receive Error Counter or Transmit Error Counter≥96).
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