UM0306 Inter-integrated circuit (I2C) interface
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15 Inter-integrated circuit (I
2
C) interface
15.1 Introduction
I
2
C (Inter-Integrated Circuit) Bus Interface serves as an interface between the
microcontroller and the serial I
2
C bus. It provides multi-master capability, and controls all I
2
C
bus-specific sequencing, protocol, arbitration and timing. It supports standard and fast
speed modes. It is also SMBus 2.0 compatible.
It may be used for a variety of purposes, including CRC generation and verification, SMBus
(System Management Bus) and PMBus (Power Management Bus).
Depending on specific device implementation DMA capability can be available for reduced
CPU overload.
15.2 Main features
● Parallel-bus/I
2
C protocol converter
● Multi-master capability: the same interface can act as Master or Slave
● I
2
C Master features:
– Clock generation
– Start and Stop generation
● I
2
C Slave features:
– Programmable I
2
C Address detection
– Dual Addressing Capability to acknowledge 2 slave addresses
– Stop bit detection
● Generation and detection of 7-bit/10-bit addressing and General Call
● Supports different communication speeds:
– Standard Speed (up to 100 kHz),
– Fast Speed (up to 400 kHz)
● Status flags:
– Transmitter/Receiver mode flag
– End-of-Byte transmission flag
–I
2
C busy flag
● Error flags:
– Arbitration lost condition for master mode
– Acknowledgement failure after address/ data transmission
– Detection of misplaced start or stop condition
– Overrun/Underrun if clock stretching is disabled
● 2 Interrupt vectors:
– 1 Interrupt for successful address/ data communication
– 1 Interrupt for error condition
● Optional Clock Stretching
● 1-byte buffer with DMA capability
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