UM0306 Inter-integrated circuit (I2C) interface
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15.6.6 Status register 1 (I2C_SR1)
Address offset: 14h
Reset Value: 0000h
151413121110987 654321 0
SMB
ALERT
TIME
OUT
Res.
PEC
ERR
OVR AF ARLO BERR TxE RxNE Res.
STOP
F
ADD10 BTF ADDR SB
rc rc rc rc rc rc rc r r r r r r r
Bit 15
SMBALERT: SMBus Alert
In SMBus host mode:
0: no SMBAlert
1: SMBAlert event occurred on pin
In SMBus slave mode:
0: no SMBAlert response address header
1: SMBAlert response address header to SMBAlert LOW received
– Cleared by software writing 0, or by hardware when PE=0.
Bit 14
TIMEOUT: Timeout or Tlow Error
0: No time-out error
1: SCL remained LOW for 25 ms (Timeout)
or
Master cumulative clock low extend time more than 10 ms (Tlow:mext)
or
Slave cumulative clock low extend time more than 25 ms (Tlow:sext)
– When set in slave mode: slave resets the communication and lines are released
by hardware
– When set in master mode: Stop condition sent by hardware
– Cleared by software writing 0, or by hardware when PE=0.
Bit 13 Reserved, forced by hardware to 0.
Bit 12
PECERR: PEC Error in reception
0: no PEC error: receiver returns ACK after PEC reception (if ACK=1)
1: PEC error: receiver returns NACK after PEC reception (whatever ACK)
– Cleared by software writing 0, or by hardware when PE=0.
Bit 11
OVR: Overrun/Underrun
0: No overrun/underrun
1: Overrun or underrun
– Set by hardware in slave mode when NOSTRETCH=1 and:
– In reception when a new byte is received (including ACK pulse) and the DR
register has not been read yet. New received byte is lost.
– In transmission when a new byte should be sent and the DR register has not
been written yet. The same byte is sent twice.
– Cleared by software writing 0, or by hardware when PE=0.
Note:
If the DR write occurs very close to SCL rising edge, the sent data is unspecified
and a hold timing error occurs
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