Inter-integrated circuit (I2C) interface UM0306
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15.6.7 Status register 2 (I2C_SR2)
Address offset: 18h
Reset Value:0000h
151413121110987 654321 0
PEC[7:0] DUALF
SMB
HOST
SMB
DEF
AULT
GEN
CALL
Res. TRA BUSY MSL
rrrrrrrrr rrr rr r
Bits 15:8
PEC[7:0] Packet Error Checking Register
This register contains the internal PEC when ENPEC=1.
Bit 7
DUALF: Dual Flag (Slave mode)
0: Received address matched with OAR1
1: Received address matched with OAR2
– Cleared by hardware after a Stop condition or repeated Start condition, or
when PE=0.
Bit 6
SMBHOST: SMBus Host Header (Slave mode)
0: No SMBus Host address
1: SMBus Host address received when SMBTYPE=1 and ENARP=1.
– Cleared by hardware after a Stop condition or repeated Start condition, or
when PE=0.
Bit 5
SMBDEFAULT: SMBus Device Default Address (Slave mode)
0: No SMBus Device Default address
1: SMBus Device Default address received when ENARP=1
– Cleared by hardware after a Stop condition or repeated Start condition, or
when PE=0.
Bit 4
GENCALL: General Call Address(Slave mode)
0: No General Call
1: General Call Address received when ENGC=1
– Cleared by hardware after a Stop condition or repeated Start condition, or
when PE=0.
Bit 3 Reserved, forced by hardware to 0.
Bit 2
TRA: Transmitter/Receiver
0: Data bytes received
1: Data bytes transmitted
This bit is set depending on R/W bit of address byte, at the end of total address
phase.
It is also cleared by hardware after detection of Stop condition (STOPF=1),
repeated Start condition, loss of bus arbitration (ARLO=1), or when PE=0.
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