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Universal synchronou
s asynchronous receive
r transmitter (USART)
UM0306
380/519
IrD
A
_RDI:
Receive Data Input
is the data input in IrD
A mode.
IrD
A
_TDO:
T
ransmit Dat
a Output in
IrD
A mode.
F
ollowing pins are
required in
modem m
ode:
nCTS:
Clear T
o Send bloc
ks the data transmission at the end
of the current transf
er when
high
nR
TS:
Request to send indicates that th
e USAR
T is ready to receiv
e a data (when low)
.
www.BDTIC.com/ST
379
381
Table of Contents
Table of Contents
2
Documentation Conventions
23
List of Abbreviations for Registers
23
Memory and Bus Architecture
24
System Architecture
24
Figure 1. System Architecture
24
Memory Organization
25
Memory Map
26
Figure 2. Memory Map
26
Peripheral Memory Map
27
Table 1. Register Boundary Addresses
27
Embedded SRAM
28
Bit Banding
29
Embedded Flash Memory
29
Table 2. Flash Module Organization
30
Boot Configuration
32
Table 3. Boot Modes
32
Power Control (PWR)
33
Power Supplies
33
Independent A/D Converter Supply and Reference Voltage
33
Figure 3. Power Supply Overview
33
Battery Backup
34
Voltage Regulator
34
Power Supply Supervisor
34
Power on Reset (Por)/Power down Reset (PDR)
34
Programmable Voltage Detector (PVD)
35
Figure 4. Power on Reset/Power down Reset Waveform
35
Figure 5. PVD Thresholds
35
Low-Power Modes
36
Slowing down System Clocks
36
Table 4. Low-Power Mode Summary
36
Peripheral Clock Gating
37
SLEEP Mode
37
Table 5. SLEEP-NOW Mode
37
STOP Mode
38
Table 6. SLEEP-ON-EXIT Mode
38
STANDBY Mode
39
Table 7. STOP Mode
39
Auto-Wake-Up (AWU) from Low-Power Mode
40
Table 8. STANDBY Mode
40
Power Control Registers
41
Power Control Register (PWR_CR)
41
Power Control/Status Register (PWR_CSR)
43
PWR Register Map
44
Table 9. PWR - Register Map and Reset Values
44
Reset and Clock Control (RCC)
45
Reset
45
System Reset
45
Power Reset
46
Backup Domain Reset
46
Clocks
46
Figure 6. Reset Circuit
46
Figure 7. Clock Tree
47
HSE Clock
48
Figure 8. HSE/ LSE Clock Sources
48
HSI Clock
49
Pll
49
LSE Clock
50
LSI Clock
50
System Clock (SYSCLK) Selection
50
Clock Security System (CSS)
51
RTC Clock
51
Watchdog Clock
51
Clock-Out Capability
51
RCC Register Description
52
Clock Control Register (RCC_CR)
52
Clock Configuration Register (RCC_CFGR)
54
Clock Interrupt Register (RCC_CIR)
57
APB2 Peripheral Reset Register (RCC_APB2RSTR)
60
APB1 Peripheral Reset Register (RCC_APB1RSTR)
62
AHB Peripheral Clock Enable Register (RCC_AHBENR)
64
APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
65
APB1 Peripheral Clock Enable Register (RCC_APB1ENR)
67
Backup Domain Control Register (RCC_BDCR)
69
Control/Status Register (RCC_CSR)
70
RCC Register Map
72
Table 10. RCC - Register Map and Reset Values
72
General Purpose and Alternate Function I/O (GPIO and AFIO)
73
GPIO Functional Description
73
General Purpose I/O (GPIO)
74
Table 12. Output Mode Bits
74
Figure 9. Basic Structure of an I/O Port Bit
74
Atomic Bit Set or Bit Reset
75
External Interrupt/Wake-Up Lines
75
Alternate Functions (AF)
75
Software Remapping of I/O Alternate Functions
76
GPIO Locking Mechanism
76
Input Configuration
76
Figure 10. Input Floating/Pull Up/Pull down Configurations
76
Output Configuration
77
Alternate Function Configuration
77
Figure 11. Output Configuration
77
Analog Input Configuration
78
Figure 12. Alternate Function Configuration
78
Figure 13. High Impedance-Analog Input Configuration
79
GPIO Register Description
80
Port Configuration Register Low (Gpiox_Crl) (X=A..e
80
Port Configuration Register High (Gpiox_Crh) (X=A..e
81
Port Input Data Register (Gpiox_Idr) (X=A..e
82
Port Output Data Register (Gpiox_Odr) (X=A..e
83
Port Bit Set/Reset Register (Gpiox_Bsrr) (X=A..e
84
Port Bit Reset Register (Gpiox_Brr) (X=A..e
85
Port Configuration Lock Register (Gpiox_Lckr) (X=A..e
86
Alternate Function I/O and Debug Configuration (AFIO)
87
Using OSC_IN/OSC_OUT Pins as GPIO Ports PD0/PD1
87
BXCAN Alternate Function Remapping
87
JTAG/SWD Alternate Function Remapping
87
Table 13. BXCAN Alternate Function Remapping
87
Table 14. Debug Interface Signals
87
Timer Alternate Function Remapping
88
Table 15. Debug Port Mapping
88
Table 16. Timer 4 Alternate Function Remapping
88
Table 17. Timer 3 Alternate Function Remapping
88
USART Alternate Function Remapping
89
Table 18. Timer 2 Alternate Function Remapping
89
Table 19. Timer 1 Alternate Function Remapping
89
Table 20. USART3 Remapping
89
I2C 1 Alternate Function Remapping
90
SPI 1 Alternate Function Remapping
90
Table 21. USART2 Remapping
90
Table 22. USART1 Remapping
90
Table 23. I2C1 Remapping
90
Table 24. SPI1 Remapping
90
AFIO Register Description
91
AF Remap and Debug I/O Configuration Register (AFIO_MAPR)
92
External Interrupt Configuration Register 1 (AFIO_EXTICR1)
95
External Interrupt Configuration Register 2 (AFIO_EXTICR2)
95
External Interrupt Configuration Register 3 (AFIO_EXTICR3)
96
External Interrupt Configuration Register 4 (AFIO_EXTICR4)
96
GPIO and AFIO Register Maps
97
GPIO Register Map
97
AFIO Register Map
97
Table 25. GPIO Register Map and Reset Values
97
Table 26. AFIO Register Map and Reset Values
97
Interrupts and Events
98
Nested Vectored Interrupt Controller (NVIC)
98
Systick Calibration Value Register
98
Interrupt and Exception Vectors
98
Table 27. Vector Table
98
External Interrupt/Event Controller (EXTI)
101
Main Features
101
Block Diagram
101
Figure 14. External Interrupt/Event Controller Block Diagram
101
Wake-Up Event Management
102
Functional Description
102
External Interrupt/Event Line Mapping
103
EXTI Register Description
103
Figure 15. External Interrupt/Event GPIO Mapping
103
EXTI Register Map
107
Table 28. External Interrupt/Event Controller Register Map and Reset Values
107
DMA Controller (DMA)
108
Introduction
108
Main Features
108
Functional Description
109
DMA Transactions
109
Figure 16. DMA Block Diagram
109
Arbiter
110
DMA Channels
110
Error Management
111
DMA Request Mapping
112
Figure 17. DMA Request Mapping
112
DMA Registers
113
DMA Interrupt Status Register (DMA_ISR)
113
Table 29. Summary of DMA Requests for each Channel
113
DMA Interrupt Flag Clear Register (DMA
115
DMA Channel X Configuration Register (Dma_Ccrx) (X = 1
116
DMA Channel X Number of Data Register (Dma_Cndtrx) (X = 1
117
DMA Channel X Peripheral Address Register (Dma_Cparx) (X = 1
118
DMA Channel X Memory Address Register (Dma_Cmarx) (X = 1
118
DMA Register Map
118
Real-Time Clock (RTC)
121
Introduction
121
Main Features
121
Functional Description
121
Overview
121
Figure 18. RTC Simplified Block Diagram
122
Resetting RTC Registers
123
Reading RTC Registers
123
Configuring RTC Registers
124
Asserting RTC Flags
124
Figure 19. RTC Second and Alarm Waveform Example with PR=0003, ALARM=00004
124
RTC Register Description
125
RTC Control Register High (RTC_CRH)
125
Figure 20. RTC Overflow Waveform Example with PR=0003
125
RTC Control Register Low (RTC_CRL)
126
RTC Prescaler Load Register (RTC_PRLH / RTC_PRLL)
128
RTC Prescaler Divider Register (RTC_DIVH / RTC_DIVL)
129
RTC Counter Register (RTC_CNTH / RTC_CNTL)
130
RTC Alarm Register High (RTC_ALRH / RTC_ALRL)
131
RTC Register Map
132
Table 31. RTC - Register Map and Reset Values
132
Backup Registers (BKP)
133
Introduction
133
Features
133
Tamper Detection
133
RTC Calibration
134
BKP Register Description
134
Backup Data Register X (Bkp_Drx) (X = 1
134
RTC Clock Calibration Register (BKP_RTCCR)
134
Backup Control Register (BKP_CR)
135
Backup Control/Status Register (BKP_CSR)
135
BKP Register Map
137
Table 32. BKP - Register Map and Reset Values
137
Independent Watchdog (IWDG)
138
Introduction
138
Hardware Watchdog
138
Register Access Protection
138
Debug Mode
138
IWDG Register Description
139
Key Register (IWDG_KR)
139
Table 33. Watchdog Time-Out Period (with 32 Khz Input Clock)
139
Figure 21. Independent Watchdog Block Diagram
139
Prescaler Register (IWDG_PR)
141
Reload Register (IWDG_RLR)
142
Status Register (IWDG_SR)
142
IWDG Register Map
144
Table 34. IWDG Register Map and Reset Values
144
Window Watchdog (WWDG)
145
Introduction
145
Main Features
145
Functional Description
145
Figure 22. Watchdog Block Diagram
145
How to Program the Watchdog Timeout
146
Debug Mode
147
Figure 23. Window Watchdog Timing Diagram
147
Register Description
148
Control Register (WWDG_CR)
148
Configuration Register (WWDG_CFR)
148
Status Register (WWDG_SR)
149
WWDG Register Map
150
Table 35. WWDG Register Map and Reset Values
150
Advanced Control Timer (TIM1)
151
Introduction
151
Main Features
151
Block Diagram
152
Figure 24. Advanced Control Timer (TIM1) Block Diagram
152
Functional Description
153
Time Base Unit
153
Counter Modes
154
Figure 25. Counter Timing Diagram with Prescaler Division Change from 1 to 2
154
Figure 26. Counter Timing Diagram with Prescaler Division Change from 1 to 4
154
Figure 27. Counter Timing Diagram, Internal Clock Divided by 1
155
Figure 28. Counter Timing Diagram, Internal Clock Divided by 2
155
Figure 29. Counter Timing Diagram, Internal Clock Divided by 4
156
Figure 30. Counter Timing Diagram, Internal Clock Divided by N
156
Figure 31. Counter Timing Diagram, Update Event When ARPE=0 (TIM1_ARR Not Preloaded)
156
Figure 32. Counter Timing Diagram, Update Event When ARPE=1 (TIM1_ARR Preloaded)
157
Figure 33. Counter Timing Diagram, Internal Clock Divided by 1
158
Figure 34. Counter Timing Diagram, Internal Clock Divided by 2
158
Figure 35. Counter Timing Diagram, Internal Clock Divided by 4
158
Figure 37. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
159
Figure 38. Counter Timing Diagram, Internal Clock Divided by 1, Tim1_Arr=0X6
160
Figure 39. Counter Timing Diagram, Internal Clock Divided by 2
160
Figure 40. Counter Timing Diagram, Internal Clock Divided by 4, Tim1_Arr=0X36
161
Figure 42. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
161
Repetition Down-Counter
162
Figure 43. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
162
Figure 44. Update Rate Examples Depending on Mode and TIM1_RCR Register Settings
163
Clock Selection
164
Figure 45. Control Circuit in Normal Mode, Internal Clock Divided by 1
164
Figure 46. TI2 External Clock Connection Example
164
Figure 47. Control Circuit in External Clock Mode 1
165
Figure 48. External Trigger Input Block
165
Capture/Compare Channels
166
Figure 49. Control Circuit in External Clock Mode 2
166
Figure 50. Capture/Compare Channel (Example: Channel 1 Input Stage)
167
Figure 51. Capture/Compare Channel 1 Main Circuit
167
Input Capture Mode
168
Figure 52. Output Stage of Capture/Compare Channel (Channel 1 to 3)
168
Figure 53. Output Stage of Capture/Compare Channel (Channel 4)
168
PWM Input Mode
169
Forced Output Mode
170
Figure 54. PWM Input Mode Timing
170
Output Compare Mode
171
PWM Mode
172
Figure 55. Output Compare Mode, Toggle on OC1
172
Figure 56. Edge-Aligned PWM Waveforms (ARR=8)
173
Complementary Outputs and Dead-Time Insertion
174
Figure 57. Center-Aligned PWM Waveforms (ARR=8)
174
Figure 58. Complementary Output with Dead-Time Insertion
175
Figure 59. Dead-Time Waveforms with Delay Greater than the Negative Pulse
175
Figure 60. Dead-Time Waveforms with Delay Greater than the Positive Pulse
175
Using the Break Function
176
Figure 61. Output Behavior in Response to a Break
178
Clearing the Ocxref Signal on an External Event
179
Figure 62. Clearing TIM1 Ocxref
179
6-Step PWM Generation
180
Figure 63. 6-Step Generation, COM Example (OSSR=1)
180
One Pulse Mode
181
Figure 64. Example of One Pulse Mode
181
Encoder Interface Mode
182
Table 36. Counting Direction Versus Encoder Signals
183
Figure 65. Example of Counter Operation in Encoder Interface Mode
184
Figure 66. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
184
Timer Input XOR Function
185
Interfacing with Hall Sensors
185
Figure 67. Example of Hall Sensor Interface
186
Timers and External Trigger Synchronization
187
Figure 68. Control Circuit in Reset Mode
187
Figure 69. Control Circuit in Gated Mode
188
Figure 70. Control Circuit in Trigger Mode
189
Timer Synchronization
190
Debug Mode
190
Figure 71. Control Circuit in External Clock Mode 2 + Trigger Mode
190
TIM1 Register Description
191
Control Register 1 (TIM1_CR1)
191
Control Register 2 (TIM1_CR2)
193
Slave Mode Control Register (TIM1_SMCR)
195
Dma/Interrupt Enable Register (TIM1_DIER)
198
Status Register (TIM1_SR)
200
Event Generation Register (TIM1_EGR)
202
Capture/Compare Mode Register 1 (TIM1_CCMR1)
204
Capture/Compare Mode Register 2 (TIM1_CCMR2)
208
Capture/Compare Enable Register (TIM1_CCER)
209
Table 37. Output Control Bits for Complementary Ocx and Ocxn Channels with Break Feature
211
Counter (TIM1_CNT)
212
Prescaler (TIM1_PSC)
212
Auto-Reload Register (TIM1_ARR)
212
Repetition Counter Register (TIM1_RCR)
213
Capture/Compare Register 1 (TIM1_CCR1)
213
Capture/Compare Register 2 (TIM1_CCR2)
214
Capture/Compare Register 3 (TIM1_CCR3)
214
Capture/Compare Register 4 (TIM1_CCR4)
215
Break and Dead-Time Register (TIM1_BDTR)
216
DMA Control Register (TIM1_DCR)
218
DMA Address for Burst Mode (TIM1_DMAR)
218
TIM1 Register Map
219
Table 38. TIM1 - Register Map and Reset Values
219
General Purpose Timer (Timx)
221
Introduction
221
Main Features
221
Block Diagram
222
Functional Description
222
Time Base Unit
222
Figure 72. General Purpose Timer Block Diagram
222
Figure 73. Counter Timing Diagram with Prescaler Division Change from 1 to 2
223
Counter Modes
224
Figure 74. Counter Timing Diagram with Prescaler Division Change from 1 to 4
224
Figure 75. Counter Timing Diagram, Internal Clock Divided by 1
225
Figure 76. Counter Timing Diagram, Internal Clock Divided by 2
225
Figure 77. Counter Timing Diagram, Internal Clock Divided by 4
225
Figure 78. Counter Timing Diagram, Internal Clock Divided by N
226
Figure 79. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
226
Figure 80. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
227
Figure 81. Counter Timing Diagram, Internal Clock Divided by 1
228
Figure 82. Counter Timing Diagram, Internal Clock Divided by 2
228
Figure 83. Counter Timing Diagram, Internal Clock Divided by 4
228
Figure 84. Counter Timing Diagram, Internal Clock Divided by N
229
Figure 85. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
229
Figure 86. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6
230
Figure 87. Counter Timing Diagram, Internal Clock Divided by 2
230
Figure 88. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
231
Figure 89. Counter Timing Diagram, Internal Clock Divided by N
231
Figure 90. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
231
Clock Selection
232
Figure 91. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
232
Figure 92. Control Circuit in Normal Mode, Internal Clock Divided by 1
233
Figure 93. TI2 External Clock Connection Example
233
Figure 94. Control Circuit in External Clock Mode 1
234
Figure 95. External Trigger Input Block
234
Capture/Compare Channels
235
Figure 96. Control Circuit in External Clock Mode 2
235
Figure 97. Capture/Compare Channel (Example: Channel 1 Input Stage)
235
Input Capture Mode
236
Figure 98. Capture/Compare Channel 1 Main Circuit
236
Figure 99. Output Stage of Capture/Compare Channel (Channel 1)
236
PWM Input Mode
237
Forced Output Mode
238
Figure 100. PWM Input Mode Timing
238
Output Compare Mode
239
PWM Mode
240
Figure 101. Output Compare Mode, Toggle on OC1
240
Figure 102. Edge-Aligned PWM Waveforms (ARR=8)
241
One Pulse Mode
242
Figure 103. Center-Aligned PWM Waveforms (ARR=8)
242
Figure 104. Example of One Pulse Mode
243
Clearing the Ocxref Signal on an External Event
244
Figure 105. Clearing Timx Ocxref
244
Table 39. Counting Direction Versus Encoder Signals
245
Figure 106. Example of Counter Operation in Encoder Interface Mode
246
Figure 107. Example of Encoder Interface Mode with IC1FP1 Polarity Inverted
246
Figure 108. Control Circuit in Reset Mode
248
Figure 109. Control Circuit in Gated Mode
249
Figure 110. Control Circuit in Trigger Mode
250
Figure 111. Control Circuit in External Clock Mode 2 + Trigger Mode
251
Figure 112. Master/Slave Timer Example
252
Figure 113. Gating Timer 2 with OC1REF of Timer 1
253
Figure 114. Gating Timer 2 with ENABLE of Timer 1
254
Figure 115. Triggering Timer 2 with UPDATE of Timer 1
254
Figure 116. Triggering Timer 2 with ENABLE of Timer 1
255
Figure 117. Triggering Timer 1 and 2 with Timer 1 TI1 Input
256
Table 40. Output Control Bit for Standard Ocx Channels
275
Table 41. Timx - Register Map and Reset Values
280
Figure 118. CAN Network Topology
283
Figure 119. CAN Block Diagram
284
Figure 120. Bxcan Operating Modes
284
Figure 121. Bxcan in Silent Mode
286
Figure 122. Bxcan in Loop Back Mode
287
Figure 123. Bxcan in Combined Mode
287
Figure 124. Transmit Mailbox States
289
Figure 125. Receive FIFO States
290
Figure 126. Filter Bank Scale Configuration - Register Organization
292
Figure 127. Example of Filter Numbering
293
Figure 128. Filtering Mechanism - Example
294
Table 42. Transmit Mailbox Mapping
295
Table 43. Receive Mailbox Mapping
295
Figure 129. CAN Error State Diagram
296
Figure 130. Bit Timing
297
Figure 131. CAN Frames
298
Figure 132. Event Flags and Interrupt Generation
299
Table 44. Bxcan - Register Map and Reset Values
324
Figure 133. I2C Bus Protocol
329
Figure 134. I2C Block Diagram
330
Figure 135. Transfer Sequence Diagram for Slave Transmitter
332
Figure 136. Transfer Sequence Diagram for Slave Receiver
333
Figure 137. Transfer Sequence Diagram for Master Transmitter
336
Figure 138. Transfer Sequence Diagram for Master Receiver
337
Table 45. Smbus Vs I2C
339
Table 46. I2C Interrupt Requests
344
Figure 139. I2C Interrupt Mapping Diagram
345
Table 47. I2C Register Map and Reset Values
358
Figure 140. SPI Block Diagram
360
Figure 141. Single Master/ Single Slave Application
361
Figure 142. Hardware/Software Slave Select Management
361
Figure 143. Data Clock Timing Diagram
363
Table 48. SPI Interrupt Requests
369
Table 49. SPI Register Map and Reset Values
376
Figure 144. USART Block Diagram
381
Figure 145. Word Length Programming
382
Figure 146. Configurable Stop Bits
384
Table 50. Noise Detection from Sampled Data
387
Figure 147. Data Sampling for Noise Detection
387
Table 51. Error Calculation for Programmed Baud Rates
390
Figure 148. Mute Mode Using Idle Line Detection
391
Figure 149. Mute Mode Using Address Mark Detection
391
Table 52. Frame Formats
392
Figure 150. Break Detection in LIN Mode (11-Bit Break Length - LBDL Bit Is Set)
394
Figure 151. Break Detection in LIN Mode Vs Framing Error Detection
395
Figure 152. USART Example of Synchronous Transmission
396
Figure 153. USART Data Clock Timing Diagram (M=0)
396
Figure 154. USART Data Clock Timing Diagram (M=1)
397
Figure 155. RX Data Setup/Hold Time
397
Figure 156. ISO 7816-3 Asynchronous Protocol
398
Figure 157. Parity Error Detection Using the 1.5 Stop Bits
399
Figure 158. Irda SIR ENDEC- Block Diagram
401
Figure 159. Irda Data Modulation (3/16) -Normal Mode
401
Figure 160. Hardware Flow Control between 2 USART
403
Figure 161. RTS Flow Control
403
Figure 162. CTS Flow Control
404
Table 53. USART Interrupt Requests
405
Figure 163. USART Interrupt Mapping Diagram
405
Table 54. USART Register Map and Reset Values
418
Figure 164. USB Peripheral Block Diagram
420
Figure 165. Packet Buffer Areas with Examples of Buffer Description Table Locations
425
Table 55. Double-Buffering Buffer Flag Definition
430
Table 56. Bulk Double-Buffering Memory Buffers Usage
430
Table 58. Resume Event Detection
433
Table 59. Reception Status Encoding
444
Table 60. Endpoint Type Encoding
445
Table 61. Endpoint Kind Meaning
445
Table 62. Transmission Status Encoding
445
Table 63. Definition of Allocated Buffer Memory
449
Table 64. USB Register Map and Reset Values
450
Figure 166. Single ADC Block Diagram
452
Figure 167. Timing Diagram
455
Figure 168. Analog Watchdog Guarded Area
455
Table 66. Analog Watchdog Channel Selection
456
Figure 169. Injected Conversion Latency
457
Figure 170. Calibration Timing Diagram
459
Figure 171. Right Alignment of Data
460
Figure 172. Left Alignment of Data
460
Table 67. External Trigger for Regular Channels
461
Table 68. External Trigger for Injected Channels
461
Figure 173. Dual ADC Block Diagram
463
Figure 174. Injected Simultaneous Mode on 4 Channels
464
Figure 175. Regular Simultaneous Mode on 16 Channels
464
Figure 176. Fast Interleaved Mode on 1 Channel in Continuous Conversion Mode
465
Figure 177. Slow Interleaved Mode on 1 Channel
466
Figure 178. Alternate Trigger: Injected Channel Group of each Adcl
466
Figure 179. Alternate Trigger: 4 Injected Channels (each ADC) in Discontinuous Model
467
Figure 180. Alternate + Regular Simultaneous
467
Figure 181. Case of Trigger Occurring During Injected Conversion
468
Figure 182. Interleaved Single Channel with Injected Sequence CH11, CH12
468
Figure 183. Temperature Sensor and VREFINT Channel Block Diagram
469
Table 69. ADC Interrupts
470
Table 70. ADC - Register Map and Reset Values
485
Figure 184. Block Diagram of Stm32F10X-Level and Cortex-M3-Level Debug Support
487
Figure 185. JTAG TAP Connections
493
Table 71. JTAG Debug Port Data Registers
494
Table 72. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]
495
Table 73. Packet Request (8-Bits)
496
Table 74. ACK Response (3 Bits)
497
Table 75. DATA Transfer (33 Bits)
497
Table 76. SW-DP Registers
498
Table 77. Main ITM Registers
502
Table 78. Important TPIU Registers
512
Table 79. DBG - Register Map and Reset Values
513
Table 80. Document Revision History
514
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ST STM32F10 Series Specifications
General
Brand
ST
Model
STM32F10 Series
Category
Microcontrollers
Language
English
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