UM0306 Universal synchronous asynchronous receiver transmitter (USART)
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Bit 5
RXNE: Read Data Register Not Empty.
This bit is set by hardware when the content of the RDR shift register has been
transferred to the USART_DR register. An interrupt is generated if RXNEIE=1 in
the USART_CR1 register. It is cleared by a read to the USART_DR register.
0: Data is not received
1: Received data is ready to be read.
Bit 4
IDLE: IDLE line detected.
This bit is set by hardware when an Idle Line is detected. An interrupt is
generated if the IDLEIE=1 in the USART_CR1 register. It is cleared by a software
sequence (an read to the USART_SR register followed by a read to the
USART_DR register).
0: No Idle Line is detected
1: Idle Line is detected
Note:
The IDLE bit will not be set again until the RXNE bit has been set itself (i.e. a new
idle line occurs)
Bit 3
ORE: OverRun Error.
This bit is set by hardware when the word currently being received in the shift
register is ready to be transferred into the RDR register while RXNE=1. An
interrupt is generated if RXNEIE=1 in the USART_CR1 register. It is cleared by a
software sequence (an read to the USART_SR register followed by a read to the
USART_DR register).
0: No Overrun error
1: Overrun error is detected
Note:
When this bit is set, the RDR register content will not be lost but the shift register
will be overwritten. An interrupt is generated on ORE flag in case of Multi Buffer
communication if the EIE bit is set.
Bit 2
NE: Noise Error Flag.
This bit is set by hardware when noise is detected on a received frame. It is
cleared by a software sequence (an read to the USART_SR register followed by
a read to the USART_DR register).
0: No noise is detected
1: Noise is detected
Note:
This bit does not generate interrupt as it appears at the same time as the RXNE bit
which itself generates an interrupting interrupt is generated on NE flag in case of
Multi Buffer communication if the EIE bit is set.
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