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ST STM32F10 Series User Manual

ST STM32F10 Series
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UM0306 Universal synchronous asynchronous receiver transmitter (USART)
415/519
17.4.6 Control register 3 (USART_CR3)
Address Offset: 14h
Reset Value: 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
1514131211109876543210
Reserved CTSIE CTSE RTSE DMAT DMAR SCEN NACK
HD
SEL
IRLP IREN EIE
rw rw rw rw rw rw rw rw rw rw rw
Bits 31:11 Reserved, forced by hardware to 0.
Bit 10
CTSIE: CTS Interrupt Enable.
0: Interrupt is inhibited
1: An interrupt is generated whenever CTS=1 in the USART_SR register
Bit 9
CTSE: CTS Enable.
0: CTS hardware flow control disabled
1: CTS mode enabled, data is only transmitted when the nCTS input is asserted
(tied to 0). If the nCTS input is deasserted while a data is being transmitted, then
the transmission is completed before stopping. If a data is written into the data
register while nCTS is asserted, the transmission is postponed until nCTS is
asserted.
Bit 8
RTSE: RTS Enable.
0: RTS hardware flow control disabled
1: RTS interrupt enabled, data is only requested when there is space in the
receive buffer. The transmission of data is expected to cease after the current
character has been transmitted. The nRTS output is asserted (tied to 0) when a
data can be received.
Bit 7
DMAT: DMA Enable Transmitter.
This bit is set/reset by software
1: DMA mode is enabled for transmission.
0: DMA mode is disabled for transmission.
Bit 6
DMAR: DMA Enable Receiver.
This bit is set/reset by software
1: DMA mode is enabled for reception.
0: DMA mode is disabled for reception.
Bit 5
SCEN: Smartcard mode enable.
This bit is used for enabling Smartcard mode.
0: Smartcard Mode disabled
1: Smartcard Mode enabled
Bit 4
NACK: Smartcard NACK enable.
0: NACK transmission in case of parity error is disabled
1: NACK transmission during parity error is enabled.
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ST STM32F10 Series Specifications

General IconGeneral
BrandST
ModelSTM32F10 Series
CategoryMicrocontrollers
LanguageEnglish

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