Universal synchronous asynchronous receiver transmitter (USART) UM0306
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Note: These 3 bits (CPOL, CPHA, LBCL) should not be written while the transmitter is enabled.
Bit 8
LBCL: Last Bit Clock pulse.
This bit allows the user to select whether the clock pulse associated with the last
data bit transmitted (MSB) has to be output on the SCLK pin in synchronous
mode.
0: The clock pulse of the last data bit is not output to the SCLK pin.
1: The clock pulse of the last data bit is output to the SCLK pin.
Note:
The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format
selected by the M bit in the USART_CR1 register.
Bit 7 Reserved, forced by hardware to 0.
Bit 6
LBDIE: LIN Break Detection Interrupt Enable.
Break interrupt mask (break detection using break delimiter).
0: Interrupt is inhibited
1: An interrupt is generated whenever LBD=1 in the USART_SR register
Bit 5
LBDL: LIN Break Detection Length.
This bit is for selection between 11 bit or 10 bit break detection.
0: 10 bit break detection
1: 11 bit break detection
Bit 4 Reserved, forced by hardware to 0.
Bits 3:0
ADD[3:0]: Address of the USART node.
This bit-field gives the address of the USART node.
This is used in multi-processor communication during mute mode, for wake up
with address mark detection.
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