USB full speed device interface (USB) UM0306
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18.6.3 Buffer descriptor table
USB PeripheralIn the following pages two location addresses are reported: the one to be
used by application software while accessing the packet memory, and the local one relative
to accessThe buffer description table entry associated with the registers is described
below. A thorough explanation of packet buffers and buffer descriptor table usage can be
found in the Structure and usage of packet buffers on page 423.
Transmission buffer address n ()
Address Offset: [] + n*16
USB local Address: [] + n*8
Transmission byte count n ()
Address Offset: [] + n*16 + 4
USB local Address: [] + n*8 + 2
Double-buffered and Isochronous IN Endpoints have two
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDRn_TX[15:1] -
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw -
Bits 15:1
ADDRn_TX[15:1]: Transmission Buffer Address
These bits point to the starting address of the packet buffer containing data to be
transmitted by the endpoint associated with the register at the next IN token addressed
to it.
Bit 0
Must always be written as ‘0’ since packet memory is word-wide and all packet buffers
must be word-aligned.
151413121110987654321 0
- COUNTn_TX[9:0]
rw rw rw rw rw rw rw rw rw rw
Bits 15:10
These bits are not used since packet size is limited by USB specifications to 1023 bytes.
Their value is not considered by the USB Peripheral.
Bits 9:0
COUNTn_TX[9:0]: Transmission Byte Count
These bits contain the number of bytes to be transmitted by the endpoint associated
with the register at the next IN token addressed to it.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
- COUNTn_TX_1[9:0]
------rwrwrwrwrwrwrwrwrwrw
151413121110987654321 0
- COUNTn_TX_0[9:0]
------rwrwrwrwrwrwrwrwrwrw
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