UM0306 Analog/digital converter (ADC)
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19.13.1 ADC status register (ADC_SR)
Address Offset: 00h
Reset value: 00000000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
1514131211109876543210
Reserved STRT JSTRT JEOC EOC AWD
rw rw rw rw rw
Bits 31:5 Reserved, must be kept cleared.
Bit 4
STRT: Regular channel Start flag
This bit is set by hardware when regular channel conversion starts. It is
cleared by software.
0: No regular channel conversion started
1: Regular channel conversion has started
Bit 3
JSTRT: Injected channel Start flag
This bit is set by hardware when injected channel group conversion starts. It is
cleared by software.
0: No injected group conversion started
1: Injected group conversion has started
Bit 2
JEOC: Injected channel end of conversion
This bit is set by hardware at the end of all injected group channel conversion.
It is cleared by software.
0: Conversion is not complete
1: Conversion complete
Bit 1
EOC: End of conversion
This bit is set by hardware at the end of a group channel conversion (regular
or injected). It is cleared by software or by reading the ADC_DR.
0: Conversion is not complete
1: Conversion complete
Bit 0
AWD: Analog watchdog flag
This bit is set by hardware when the converted voltage crosses the values
programmed in the ADC_LTR and ADC_HTR registers. It is cleared by
software.
0: No Analog Watchdog event occurred
1: Analog Watchdog event occurred
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