UM0306 Analog/digital converter (ADC)
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Bit 21
JSWSTART: Start Conversion of injected channels
This bit is set by software and cleared by software or by hardware as soon as
the conversion starts. It starts a conversion of a a group of injected channels
(if JSWSTART is selected as trigger event by the JEXTSEL[2:0] bits.
0: Reset state
1: Starts conversion of injected channels
Bit 20
EXTTRIG: External Trigger Conversion mode for regular channels
This bit is set and cleared by software to enable/disable the external trigger
used to start conversion of a regular channel group.
0: Conversion on external event disabled
1: Conversion on external event enabled
Bits 19:17
EXTSEL[2:0]: External Event Select for regular group
These bits select the external event used to trigger the start of conversion of a
regular group:
000: Timer 1 CC1 event
001: Timer 1 CC2 event
010: Timer 1 CC3 event
011: Timer 2 CC2 event
100: Timer 3 TRGO event
101: Timer 4 CC4 event
110: External interrupt 11
111: SWSTART
Bit 16 Reserved, must be kept cleared.
Bit 15
JEXTTRIG: External Trigger Conversion mode for injected channels
This bit is set and cleared by software to enable/disable the external trigger
used to start conversion of an injected channel group.
0: Conversion on external event disabled
1: Conversion on external event enabled
Bits 14:12
JEXTSEL[2:0]: External event select for injected group
These bits select the external event used to trigger the start of conversion of
an injected group:
000: Timer 1 TRGO event
001: Timer 1 CC4 event
010: Timer 2 TRGO event
011: Timer 2 CC1 event
100: Timer 3 CC4 event
101: Timer 4 TRGO event
110: External interrupt 15
111: JSWSTART
Bit 11
ALIGN: Data Alignment
This bit is set and cleared by software. Refer to Figure 171.and Figure 172.
0: Right Alignment
1: Left Alignment
Bits 10:9 Reserved, must be kept cleared.
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