Analog/digital converter (ADC) UM0306
476/519
Bit 8
DMA: Direct Memory access mode
This bit is set and cleared by software. Refer to the DMA controller chapter for
more details.
0: DMA mode disabled
1: DMA mode enabled
Note: In devices with more that one ADC, only ADC1 can generate a DMA
request.
Bits 7:4 Reserved, must be kept cleared.
Bit 3
RSTCAL: Reset Calibration
This bit is reset by software and cleared by hardware. It sets the calibration
registers in the Analog ADC block and the CAL signal to the ADC. This bit will
be cleared after the calibration registers are cleared.
0: Calibration register initialized.
1: Initialize calibration register.
Note: If RSTCAL is reset when conversion is ongoing extra cycles are required
for clearing the calibration register
Bit 2
CAL: A/D Calibration
This bit is set by software to start the calibration. It is reset by hardware after
calibration is complete.
0: Calibration completed
1: Enable calibration
Bit 1
CONT: Continuous Conversion
This bit is set and cleared by software. If set conversion takes place
continuously till this bit is reset.
0: Single conversion mode
1: Continuous conversion mode
Bit 0
ADON: A/D Converter ON / OFF
This bit is set and cleared by software. If this bit holds a value of zero and a 1
is written to it then it wakes up the ADC from Power Down state.
Conversion starts when this bit holds a value of 1 and a 1 is written to it. The
application should allow a delay of t
STAB
between power up and start of
conversion. Refer to Figure 167.
0: Disable ADC conversion/calibration and go to power down mode.
1: Enable ADC and to start conversion
Note: If any other bit in this register apart from ADON is changed at the same
time, then conversion is not triggered. This is to prevent triggering an erroneous
conversion.
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