Analog/digital converter (ADC) UM0306
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19.13.13 ADC injected data register x (ADC_JDRx) (x= 1..4)
Address offset: 3C - 48h
Reset value: 0000 0000h
19.13.14 ADC regular data register (ADC_DR)
Address offset: 4Ch
Reset value: 0000 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
1514131211109876543210
JDATA[15:0]
rrrrrrr r r rrrrrrr
Bits 31:16 Reserved, must be kept cleared.
Bits 15:0
JDATA[15:0]: Injected data
These bits are read only. They contain the conversion result from injected
channel x. The data is left or right-aligned as shown in Figure 171 and
Figure 172.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADC2DATA[15:0]
rrrrrrr r r rrrrrrr
1514131211109876543210
DATA[15:0]
rrrrrrr r r rrrrrrr
Bits 31:16
ADC2DATA[15:0]: ADC2 data
– In ADC1: In dual mode, these bits contain the regular data of ADC2. Refer to
Section 19.10: Dual ADC mode
– In ADC2: these bits are not used
Bits 15:0
DATA[15:0]: Regular data
These bits are read only. They contain the conversion result from the regular
channels. The data is left or right-aligned as shown in Figure 171 and
Figure 172.
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