UM0306 Debug support (DBG)
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Bits 31:15 Reserved, must be kept cleared.
Bit 14
DBG_CAN_STOP: Debug CAN stopped when Core is halted
0: Same behavior as in normal mode.
1: The CAN receive registers are frozen.
Bits 13:10
DBG_TIMx_STOP: Regular data. x=4..1
0: The clock of the involved Timer Counter is fed even if the core is halted.
1: The clock of the involved Timer counter is stopped when the core is halted.
Bit 9
DBG_WWDG_STOP: Debug Window Watchdog stopped when Core is halted
0: The Window Watchdog Counter clock continues even if the core is halted.
1: The Window Watchdog Counter clock is stopped when the core is halted.
Bit 8
DBG_IWDG_STOP: Debug Independent Watchdog stopped when Core is
halted
0: The Watchdog counter clock continues even if the core is halted.
1: The Watchdog counter clock is stopped when the core is halted.
Bits 7:5
TRACE_MODE[1:0] and TRACE_IOEN: Trace Pin Assignment Control
– With TRACE_IOEN=0:
TRACE_MODE=xx: TRACE pins not assigned (default state)
– With TRACE_IOEN=1:
TRACE_MODE=00: TRACE pin assignment for Asynchronous Mode
TRACE_MODE=01: TRACE pin assignment for Synchronous Mode with a
TRACEDATA size of 1
TRACE_MODE=10: TRACE pin assignment for Synchronous Mode with a
TRACEDATA size of 2
TRACE_MODE=11: TRACE pin assignment for Synchronous Mode with a
TRACEDATA size of 4
Bit 4:3 Reserved, must be kept cleared.
Bit 2
DBG_STANDBY: Debug Standby mode
0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
From software point of view, exiting from STANDBY is identical than fetching
reset vector (except a few status bit indicated that the MCU is resuming from
STANDBY)
1: (FCLK=On, HCLK=On) In this case, the digital part is not unpowered and
FCLK and HCLK are provided by the internal RC oscillator which remains
active. In addition, the MCU generate a system reset during STANDBY mode
so that exiting from STANDBY is identical than fetching from reset
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