Debug support (DBG) UM0306
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20.16 TPIU (trace port interface unit)
20.16.1 Introduction
The TPIU acts as a bridge between the on-chip trace data from the ITM.
The output data stream encapsulates the trace source ID, that is then captured by a Trace
Port Analyzer (TPA).
The core embeds a simple TPIU, especially designed for low-cost debug (consisting of a
special version of the CoreSight TPIU).
The TPIU only supports ITM debug trace which is a limited trace as it only outputs
information coming from the ITM.
Bit 1
DBG_STOP: Debug Stop Mode
0: (FCLK=Off, HCLK=Off) In STOP mode, the clock controller disables all
clocks (including HCLK and FCLK). When exiting from STOP mode, the clock
configuration is identical to the one after RESET (CPU clocked by the 8 MHz
internal RC oscillator (HSI)). Consequently, the software must reprogram the
clock controller to enable the PLL, the Xtal, etc.
1: (FCLK=On, HCLK=On) In this case, when entering STOP mode, FCLK and
HCLK are provided by the internal RC oscillator which remains active in STOP
mode. When exiting STOP mode, the software must reprogram the clock
controller to enable the PLL, the Xtal, etc. (in the same way it would do in case
of DBG_STOP=0)
Bit 0
DBG_SLEEP: Debug Sleep Mode
0: (FCLK=On, HCLK=Off) In SLEEP mode, FCLK is clocked by the system
clock as previously configured by the software while HCLK is disabled.
In SLEEP mode, the clock controller configuration is not reset and remains in
the previously programmed state. Consequently, when exiting from SLEEP
mode, the software does not need to reconfigure the clock controller.
1: (FCLK=On, HCLK=On) In this case, when entering SLEEP mode, HCLK is
fed by the same clock that is provided to FCLK (system clock as previously
configured by the software).
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