ST STM32F10 Series User Manual

UM0306 Reset and clock control (RCC)
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Bits 21:18
PLLMUL PLL Multiplication Factor
These bits are written by software to define the PLL multiplication factor. These
bits can be written only when PLL is disabled.
Caution: The PLL output frequency must not exceed 72 MHz.
0000: PLL input clock x 2
0001: PLL input clock x 3
0010: PLL input clock x 4
0011: PLL input clock x 5
0100: PLL input clock x 6
0101: PLL input clock x 7
0110: PLL input clock x 8
0111: PLL input clock x 9
1000: PLL input clock x 10
1001: PLL input clock x 11
1010: PLL input clock x 12
1011: PLL input clock x 13
1100: PLL input clock x 14
1101: PLL input clock x 15
1110: PLL input clock x 16
1111: PLL input clock x 16
Bit 17
PLLXTPRE HSE divider for PLL entry
Set and reset by software to divide HSE before PLL entry. This bit can be written
only when PLL is disabled.
0: HSE clock not divided
1: HSE clock divided by 2
Bit 16
PLLSRC PLL entry clock source
Set and reset by software to select PLL clock source. This bit can be written only
when PLL is disabled.
0: HSI oscillator clock / 2 selected as PLL input clock
1: HSE oscillator clock selected as PLL input clock
Bits 14:12
ADCPRE ADC prescaler
Set and reset by software to select the frequency of the clock to the ADCs.
00: PLCK2 divided by 2
01: PLCK2 divided by 4
10: PLCK2 divided by 6
11: PLCK2 divided by 8
Bits 13:11
PPRE2 APB High speed prescaler (APB2)
Set and reset by software to control APB High speed clocks division factor.
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
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ST STM32F10 Series Specifications

General

Brand	ST
Model	STM32F10 Series
Category	Microcontrollers
Language	English