Reset and clock control (RCC) UM0306
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Bits 10:8
PPRE1 APB Low speed prescaler (APB1)
Set and reset by software to control APB Low speed clocks division factor.
Warning: the software has to set correctly these bits to not exceed 36 MHz on this
domain.
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
Bits 7:4
HPRE AHB prescaler
Set and reset by software to control AHB clock division factor.
0xxx: SYSCLK not divided
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512
Bits 3:2
SWS System Clock Switch Status
Set and reset by hardware to indicate which clock source is used as system clock.
00: HSI oscillator used as system clock
01: HSE oscillator used as system clock
10: PLL used as system clock
11: not applicable
Bits 1:0
SW System clock Switch
Set and reset by software to select SYSCLK source.
Set by hardware to force HSI selection when leaving STOP and STANDBY mode
or in case of failure of the HSE oscillator used directly or indirectly as system
clock (if the Clock Security System is enabled).
00: HSI selected as system clock
01: HSE selected as system clock
10: PLL selected as system clock
11: not allowed
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