18 AMCC Proprietary
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
How to Use This Book
This book describes the PPC405 device architecture, programming model, external interfaces, internal registers,
and instruction set. This book is organized as follows:
• Overview on page 21
• Programming Model on page 31
• Cache Operations on page 69
• Memory Management on page 91
• Interrupt Handling on page 109
• On-Chip Memory (OCM) on page 85
• Timer Facilities on page 129
• Debugging on page 137
• Instruction Set on page 157
• Register Summary on page 353
This book contains the following appendixes:
• Instruction Summary on page 357
• Instructions by Category on page 395
• Code Optimization and Instruction Timings on page 430
To help readers find material in these chapters, the book contains:
• Contents on page 3
• Figures on page 11
• Tables on page 13
• Index on page 437
To Next Page
Loading...