AMCC Proprietary 236
Revision 1.02 - September 10, 2007
PPC405 Processor
lhzux
Load Halfword and Zero with Update Indexed
Preliminary User’s Manual
lhzux
Load Halfword and Zero with Update Index ed
EA ← (RA) + (RB)
(RA)
← EA
(RT)
←
16
0 || MS(EA,2)
An effective address (EA) is formed by adding an index to the base address in register RA. The index is the
contents of register RB. The EA is placed into register RA.
The halfword at the EA is extended to 32 bits by concatenating 16 0-bits to its left. The result is placed into register
RT.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
•RA
•RT
Invalid Instruction Forms
• Reserved fields
•RA=RT
•RA=0
Architecture Note
This instruction is part of the PowerPC User Instruction Set Architecture.
l
hzux RT, RA, RB
31 RT RA RB 311
0 6 11 16 21 31
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