AMCC PPC405 - Page 260

AMCC Proprietary 260
Revision 1.02 - September 10, 2007
PPC405 Processor
maclhwu
Multiply Accumulate Low Halfword to Word Modulo Unsigned
Preliminary User’s Manual
maclhwu
Multiply Accumulate Low Halfword to Word Modulo Unsign ed
prod
0:31
← (RA)
16:31
x (RB)
16:31
unsigned
temp
0:32
← prod
0:31
+ (RT)
(RT)
← temp
1:32
The low-order halfword of RA is multiplied by the low-order halfword of RB. The unsigned product is summed with
the contents of RT and the sum is stored in a 33-bit temporary register. The contents of RT are replaced by the
low-order 32 bits of the temporary register.
Registers Altered
•RT
• CR[CR0]
LT, GT, EQ, SO
if Rc contains 1
• XER[SO, OV] if OE contains 1
Architecture Note
This instruction is part of the Multiply-Accumulate instruction set extensions and complies with the architectural
requirements for APUs of the PowerPC Embedded Environment. As such, it is not part of the PowerPC Architec-
ture, nor is it part of the PowerPC Embedded Environment. Programs that use this instruction may not be portable
to other implementations.
maclhwu RT, RA, RB OE=0, Rc=0
maclhwu. RT, RA, RB OE=0, Rc=1
maclhwuo RT, RA, RB OE=1, Rc=0
maclhwuo. RT, RA, RB OE=1, Rc=1
4RTRARBOE396Rc
0 6 11 16 21 22 31