AMCC Proprietary 298
Revision 1.02 - September 10, 2007
PPC405 Processor
rfi
Return From Interrupt
Preliminary User’s Manual
rfi
Return From Interrupt
(PC) ← (SRR0)
(MSR)
← (SRR1)
The program counter (PC) is restored with the contents of SRR0 and the MSR is restored with the contents of
SRR1.
Instruction execution returns to the address contained in the PC.
Registers Altered
•MSR
Invalid Instruction Forms
• Reserved fields
Programming Note
Execution of this instruction is privileged and context-synchronizing.
Architecture Note
This instruction is part of the PowerPC Embedded Operating Environment.
rfi
19
50
0 6 21 31
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