AMCC PPC405 - Page 319

AMCC Proprietary 319
Revision 1.02 - September 10, 2007
PPC405 Processor
stswx
Store String Word Indexed
Preliminary User’s Manual
stswx
Store String Word Indexed
EA ← (RA|0) + (RB)
n
← XER[TBC]
r
← RS – 1
i ← 0
dowhilen>0
if i = 0 then
r
← r+1
if r = 32 then
r
← 0
MS(EA, 1)
← (GPR(r)
i:i+7
)
i
← i+8
if i = 32 then
i
← 0
EA
← EA + 1
n
← n–1
An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
The base address is 0 when the RA field is 0, and is the contents of register RA otherwise.
A byte count is contained in XER[TBC].
The contents of a series of consecutive GPRs (starting with register RS, continuing through GPR(31), wrapping to
GPR(0), and continuing to the final byte count) are stored, starting at the EA. The bytes in each GPR are accessed
starting with the most significant byte. The byte count determines the number of transferred bytes.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
•None
Invalid Instruction Forms
• Reserved fields
Programming Note
If XER[TBC] = 0, stswx is treated as a no-op.
The PowerPC Architecture states that if XER[TBC] = 0 and if the EA is such that a precise data exception would
normally occur (if not for the zero length), stswx is treated as a no-op and the precise exception will not occur.
Data storage exceptions and alignment exceptions are examples of precise data exceptions.
However, the architecture makes no statement regarding imprecise exceptions related to stswx when
XER[TBC] = 0. PowerPC processors generate an imprecise exception (machine check) on this instruction when all
of the following conditions are true:
• The instruction passes all protection bounds checking
• The address is cacheable
stswx RS, RA, RB
31 RS RA RB 661
0 6 11 16 21 31