AMCC PPC405 - Page 335

AMCC Proprietary 335
Revision 1.02 - September 10, 2007
PPC405 Processor
tlbre
TLB Read Entry
Preliminary User’s Manual
tlbre
TLB Read Entry
if WS
4
= 1
(RT)
← TLBLO[(RA
26:31
)]
else
(RT)
← TLBHI[(RA
26:31
)]
(PID)
← TID from TLB[(RA
26:31
)]
The contents of the selected TLB entry is placed into register RT (and possibly into PID).
Bits 26:31 of the contents of RA is used as an index into the TLB. If this index specifies a TLB entry that does not
exist, the results are undefined.
The WS field specifies which portion (TLBHI or TLBLO) of the entry is loaded into RT. If TLBHI is being accessed,
the PID SPR is set to the value of the TID field in the TLB entry.
If the WS field is not 0 or 1, the instruction form is invalid and the result is undefined.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
•RT
• PID (if
WS = 0)
Invalid Instruction Forms
• Reserved fields
• Invalid WS value
Programming Notes
This instruction is privileged. Translation is not required to be active during the execution of this instruction.
The contents of RT after the execution of this instruction are interpreted as follows:
If WS = 0 (TLBHI):
RT[0:21] ← EPN[0:21]
RT[22:24] ← SIZE[0:2]
RT[25] ← V
RT[26] ← E
RT[27] ← U0
RT[28:31] ← 0
PID[24:31] ← TID[0:7]; (note that the TID is copied to the PID, not to RT)
If WS = 1 (TLBLO):
RT[0:21]
← RPN[0:21]
RT[22:23] ← EX,WR
RT[24:27] ← ZSEL[0:3]
RT[28:31] ← WIMG
tlbre RT, RA, WS
31 RT RA WS 946
0 6 11 16 21 31