AMCC PPC405 - Page 337

AMCC Proprietary 337
Revision 1.02 - September 10, 2007
PPC405 Processor
tlbsx
TLB Search Indexed
Preliminary User’s Manual
tlbsx
TLB Search Indexed
EA ← (RA|0) + (RB)
if Rc = 1
CR[CR0]
LT
← 0
CR[CR0]
GT
← 0
CR[CR0]
SO
← XER[SO]
if Valid TLB entry matching EA and PID is in the TLB then
(RT)
← Index of matching TLB Entry
if Rc = 1
CR[CR0]
EQ
← 1
else
(RT) Undefined
if Rc = 1
CR[CR0]
EQ
← 0
An effective address is formed by adding an index to a base address. The index is the contents of register RB. The
base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
The TLB is searched for a valid entry which translates EA and PID. See XREF for details. The record bit (Rc) spec-
ifies whether the results of the search will affect CR[CR0] as shown above. The intention is that CR[CR0]
EQ
can be
tested after a tlbsx. instruction if there is a possibility that the search may fail.
Registers Altered
• CR[CR0]
LT, GT, EQ, SO
if Rc contains 1
Invalid Instruction Forms
• None.
Programming Note
This instruction is privileged. Translation is not required to be active during the execution of this instruction.
Architecture Note
This instruction part of the PowerPC Embedded Operating Environment.
tlbsx RT, RA, RB Rc=0
tlbsx. RT, RA, RB Rc=1
31 RT RA RB 914 Rc
0 6 11 16 21 31