AMCC Proprietary 339
Revision 1.02 - September 10, 2007
PPC405 Processor
tlbwe
TLB Write Entry
Preliminary User’s Manual
tlbwe
TLB Write Entry
if WS
4
= 1
TLBLO[(RA
26:31
)] ← (RS)
else
TLBHI[(RA
26:31
)] ←
(RS)
TID of TLB[(RA
26:31
)] ← (PID
24:31
)
The contents of the selected TLB entry is replaced with the contents of register RS (and possibly PID).
Bits 26:31 of the contents of RA are used as an index into the TLB. If this index specifies a TLB entry that does not
exist, the results are undefined.
The WS field specifies which portion (TLBHI or TLBLO) of the entry is replaced from RS. For instructions that
specify TLBHI, the TID field in the TLB entry is supplied from PID
24:31.
If the WS field is not 0 or 1, the instruction form is invalid and the result is undefined.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• None.
Invalid Instruction Forms
• Reserved fields
• Invalid WS value
Programming Notes
This instruction is privileged. Translation is not required to be active during the execution of this instruction.
The effects of this update are not guaranteed to be visible to the programming model until the completion of a
context synchronizing operation. For example, updating a zone selection field within the TLB while in supervisor
code should be followed by an isync instruction (or other context synchronizing operation) to guarantee that the
desired translation and protection domains are used.
tlbwe writes the TLB fields from RS and the PID as follows:
If WS = 0 (TLBHI):
EPN[0:21] ←
RS[0:21]
SIZE[0:2] ←
RS[22:24]
V
←
RS[25]
E ←
RS[26]
U0 ←
RS[27]
TID[0:7] ←
PID[24:31]; (note that the TID is written from the PID, not RS)
If WS = 1 (TLBLO):
RPN[0:21]
←
RT[0:21]
EX,WR ←
RS[22:23]
ZSEL[0:3] ←
RS[24:27]
WIMG ←
RS[28:31]
tlbwe RS, RA, WS
31 RS RA WS 978
0 6 11 16 21 31
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