AMCC PPC405 - Page 341

AMCC Proprietary 341
Revision 1.02 - September 10, 2007
PPC405 Processor
tw
Trap Word
Preliminary User’s Manual
tw
Trap Word
if ( ((RA) (RB) ∧ TO
0
=1) ∨
((RA) (RB)
∧ TO
1
=1) ∨
((RA) (RB)
∧ TO
2
=1) ∨
((RA) (RB) ∧ TO
3
=1) ∨
((RA) (RB)
∧ TO
4
= 1) ) then TRAP (see details below)
Register RA is compared with register RB. If any comparison condition selected by the TO field is true, a TRAP
occurs. The behavior of a TRAP depends upon the debug mode of the processor, as described below:
• If TRAP is not enabled as a debug event (DBCR[TDE] = 0 or DBCR[EDM,IDM] = 0,0):
TRAP causes a program interrupt. See Program Interrupt on page 123.
(SRR0) ← address of tw instruction
(SRR1) ← (MSR)
(ESR[PTR]) ← 1
(MSR[WE, EE, PR, DR, IR]) ← 0
PC ← EVPR
0:15
|| 0x0700
• If TRAP is enabled as an external debug event (DBCR[TDE] = 1 and DBCR[EDM] = 1):
TRAP goes to the debug stop state, to be handled by an external debugger with hardware control.
(DBSR[TIE]) ← 1
In addition, if TRAP is also enabled as an internal debug event (DBCR[IDM] = 1)
and debug exceptions are disabled (MSR[DE] = 0), then report an imprecise event:
(DBSR[IDE]) ← 1
PC
← address of tw instruction
• If TRAP is enabled as an internal debug event and not an external debug event (DBCR[TDE] = 1 and
DBCR[EDM,IDM] = 0,1) and debug exceptions are enabled (MSR[DE] = 1):
TRAP causes a debug interrupt. See Debug Interrupt on page 128.
(SRR2) ← address of tw instruction
(SRR3)
← (MSR)
(DBSR[TIE])
← 1
(MSR[WE, EE, PR, CE, DE, DR, IR])
← 0
PC
← EVPR
0:15
|| 0x2000
• If TRAP is enabled as an internal debug event and not an external debug event (DBCR[TDE] = 1 and
DBCR[EDM,IDM] = 0,1) and Debug Exceptions are disabled (MSR[DE] = 0):
TRAP reports the debug event as an imprecise event and causes a program interrupt. See Program Interrupt on
page 123.
(SRR0) ← address of tw instruction
(SRR1) ← (MSR)
(ESR[PTR])
← 1
(DBSR[TIE,IDE])
← 1,1
(MSR[WE, EE, PR, DR, IR]) ← 0
PC
← EVPR
0:15
|| 0x0700
tw TO, RA, RB
31 TO RA RB 4
0 6 11 16 21 31
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