AMCC PPC405 - Page 418

AMCC Proprietary 418
Revision 1.02 - September 10, 2007
PPC405 Processor
Preliminary User’s Manual
Table B-6. Storage Reference Instructions
Mnemonic Operands Function
Other Registers
Changed
Page
lbz RT, D(RA) Load byte from EA = (RA|0) + EXTS(D) and pad left with zeroes,
(RT)
←
24
0 || MS(EA,1).
225
lbzu RT, D(RA) Load byte from EA = (RA|0) + EXTS(D) and pad left with zeroes,
(RT)
←
24
0 || MS(EA,1).
Update the base address,
(RA)
← EA.
226
lbzux RT, RA, RB Load byte from EA = (RA|0) + (RB) and pad left with zeroes,
(RT)
←
24
0 || MS(EA,1).
Update the base address,
(RA)
← EA.
227
lbzx RT, RA, RB Load byte from EA = (RA|0) + (RB) and pad left with zeroes,
(RT)
←
24
0 || MS(EA,1).
228
lha RT, D(RA) Load halfword from EA = (RA|0) + EXTS(D) and sign extend,
(RT)
← EXTS(MS(EA,2)).
229
lhau RT, D(RA) Load halfword from EA = (RA|0) + EXTS(D) and sign extend,
(RT) ← EXTS(MS(EA,2)).
Update the base address,
(RA)
← EA.
230
lhaux RT, RA, RB Load halfword from EA = (RA|0) + (RB) and sign extend,
(RT) ← EXTS(MS(EA,2)).
Update the base address,
(RA)
← EA.
231
lhax RT, RA, RB Load halfword from EA = (RA|0) + (RB) and sign extend,
(RT) ← EXTS(MS(EA,2)).
232
lhbrx RT, RA, RB Load halfword from EA = (RA|0) + (RB), then reverse byte order and
pad left with zeroes,
(RT)
←
16
0 || MS(EA+1,1) || MS(EA,1).
233
lhz RT, D(RA) Load halfword from EA = (RA|0) + EXTS(D) and pad left with
zeroes,
(RT)
←
16
0|| MS(EA,2).
234
lhzu RT, D(RA) Load halfword from EA = (RA|0) + EXTS(D) and pad left with
zeroes,
(RT)
←
16
0|| MS(EA,2).
Update the base address,
(RA)
← EA.
235
lhzux RT, RA, RB Load halfword from EA = (RA|0) + (RB) and pad left with zeroes,
(RT)
←
16
0|| MS(EA,2).
Update the base address,
(RA)
← EA.
236
lhzx RT, RA, RB Load halfword from EA = (RA|0) + (RB) and pad left with zeroes,
(RT)
←
16
0|| MS(EA,2).
237
lmw RT, D(RA) Load multiple words starting from EA = (RA|0) + EXTS(D).
Place into consecutive registers, RT through GPR(31).
RA is not altered unless RA = GPR(31).
238
lswi RT, RA, NB Load consecutive bytes from EA = (RA|0).
Number of bytes
n = 32 if NB = 0, else n =NB.
Stack bytes into words in CEIL(n/4)
consecutive registers starting with RT, to
R
FINAL
← ((RT + CEIL(n/4) – 1) % 32).
GPR(0) is consecutive to GPR(31).
RA is not altered unless RA = R
FINAL
.
239