AMCC PPC405 - Page 439

AMCC Confidential and Proprietary 439
Revision 1.02 - September 10, 2007
Preliminary User’s Manual
PPC405 Processor
cmpl 190
cmpli 191
cmplw 190
cmplwi
191
cmpw 188
cmpwi
189
cntlzw 192
cntlzw. 192
code optimization
430
conditional branches
mnemonics used to control prediction 53
conventions
19
CR 39, 353
crand 193
crandc
194
crclr 200
creqv 195
critical input interrupts
register settings
118
crmove 198
crnand
196
crnor 197
crnot 197
cror
198
crorc 199
crset 195
crxor
200
CTR 36
D
DAC1–DAC2 147
data alignment
42
data storage interrupts
register settings 121
data type
42
DBCRx
143
DBSR 145
dcba
functions
76
dcbf
203
functions
76
dcbi
204
functions
76
dcbst
205
functions
76
dcbt
206
functions
77
dcbtst
functions
77
dcbz
208
functions
77
dccci
210
functions
77
DCCR
106
DCR
42
dcread
211
functions 77
DCU (data cache unit)
priority changes 82
tag information in GPRs 81
DCWR
106
DEAR 118
debugging
137
boundary scan chain 138
debug interfaces 137
JTAG test access port
137
trace status port 139
development tools 137
events
147
modes 139
external 140
internal
140
real-time trace 141
wait 140
processor control
142
processor status 142
registers 142
device control registers
356
divw 213
divw. 213
divwo
213
divwo. 213
divwu 214
divwu.
214
divwuo 214
divwuo. 214
DTLB (data translation lookaside buffer)
miss interrupts
100
DVC1–DVC2 147
E
eieio 215
eqv
216
eqv. 216
ESR
116
ESR (Exception Status Register)
usage for program interrupts
123
EVPR
116
exceptions
defined 109
registers during debug exceptions
128
exceptions. See also interrupts
extended memonics
beqlr
185
extended menmonics
blectrl
182
bnlctrl
183
extended mnemonicd
bngla
179
extended mnemonics
alphabetical 402
bctr
181
bctrl
181
bdnz 176